1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Socionext SPI flash controller F_OSPI driver
4 * Copyright (C) 2021 Socionext Inc.
5 */
6
7 #include <clk.h>
8 #include <common.h>
9 #include <dm.h>
10 #include <dm/device_compat.h>
11 #include <linux/bitfield.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <spi.h>
15 #include <spi-mem.h>
16
17 /* Registers */
18 #define OSPI_PROT_CTL_INDIR 0x00
19 #define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30)
20 #define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28)
21 #define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26)
22 #define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24)
23 #define OSPI_PROT_MODE_SINGLE 0
24 #define OSPI_PROT_MODE_DUAL 1
25 #define OSPI_PROT_MODE_QUAD 2
26 #define OSPI_PROT_MODE_OCTAL 3
27 #define OSPI_PROT_DATA_RATE_DATA BIT(23)
28 #define OSPI_PROT_DATA_RATE_ALT BIT(22)
29 #define OSPI_PROT_DATA_RATE_ADDR BIT(21)
30 #define OSPI_PROT_DATA_RATE_CODE BIT(20)
31 #define OSPI_PROT_SDR 0
32 #define OSPI_PROT_DDR 1
33 #define OSPI_PROT_BIT_POS_DATA BIT(19)
34 #define OSPI_PROT_BIT_POS_ALT BIT(18)
35 #define OSPI_PROT_BIT_POS_ADDR BIT(17)
36 #define OSPI_PROT_BIT_POS_CODE BIT(16)
37 #define OSPI_PROT_SAMP_EDGE BIT(12)
38 #define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10)
39 #define OSPI_PROT_DATA_UNIT_1B 0
40 #define OSPI_PROT_DATA_UNIT_2B 1
41 #define OSPI_PROT_DATA_UNIT_4B 3
42 #define OSPI_PROT_TRANS_DIR_WRITE BIT(9)
43 #define OSPI_PROT_DATA_EN BIT(8)
44 #define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5)
45 #define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2)
46 #define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0)
47
48 #define OSPI_CLK_CTL 0x10
49 #define OSPI_CLK_CTL_BOOT_INT_CLK_EN BIT(16)
50 #define OSPI_CLK_CTL_PHA BIT(12)
51 #define OSPI_CLK_CTL_PHA_180 0
52 #define OSPI_CLK_CTL_PHA_90 1
53 #define OSPI_CLK_CTL_DIV GENMASK(9, 8)
54 #define OSPI_CLK_CTL_DIV_1 0
55 #define OSPI_CLK_CTL_DIV_2 1
56 #define OSPI_CLK_CTL_DIV_4 2
57 #define OSPI_CLK_CTL_DIV_8 3
58 #define OSPI_CLK_CTL_INT_CLK_EN BIT(0)
59
60 #define OSPI_CS_CTL1 0x14
61 #define OSPI_CS_CTL2 0x18
62 #define OSPI_SSEL 0x20
63 #define OSPI_CMD_IDX_INDIR 0x40
64 #define OSPI_ADDR 0x50
65 #define OSPI_ALT_INDIR 0x60
66 #define OSPI_DMY_INDIR 0x70
67 #define OSPI_DAT 0x80
68 #define OSPI_DAT_SWP_INDIR 0x90
69
70 #define OSPI_DAT_SIZE_INDIR 0xA0
71 #define OSPI_DAT_SIZE_EN BIT(15)
72 #define OSPI_DAT_SIZE_MASK GENMASK(10, 0)
73 #define OSPI_DAT_SIZE_MAX (OSPI_DAT_SIZE_MASK + 1)
74
75 #define OSPI_TRANS_CTL 0xC0
76 #define OSPI_TRANS_CTL_STOP_REQ BIT(1) /* RW1AC */
77 #define OSPI_TRANS_CTL_START_REQ BIT(0) /* RW1AC */
78
79 #define OSPI_ACC_MODE 0xC4
80 #define OSPI_ACC_MODE_BOOT_DISABLE BIT(0)
81
82 #define OSPI_SWRST 0xD0
83 #define OSPI_SWRST_INDIR_WRITE_FIFO BIT(9) /* RW1AC */
84 #define OSPI_SWRST_INDIR_READ_FIFO BIT(8) /* RW1AC */
85
86 #define OSPI_STAT 0xE0
87 #define OSPI_STAT_IS_AXI_WRITING BIT(10)
88 #define OSPI_STAT_IS_AXI_READING BIT(9)
89 #define OSPI_STAT_IS_SPI_INT_CLK_STOP BIT(4)
90 #define OSPI_STAT_IS_SPI_IDLE BIT(3)
91
92 #define OSPI_IRQ 0xF0
93 #define OSPI_IRQ_CS_DEASSERT BIT(8)
94 #define OSPI_IRQ_WRITE_BUF_READY BIT(2)
95 #define OSPI_IRQ_READ_BUF_READY BIT(1)
96 #define OSPI_IRQ_CS_TRANS_COMP BIT(0)
97 #define OSPI_IRQ_ALL \
98 (OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \
99 | OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP)
100
101 #define OSPI_IRQ_STAT_EN 0xF4
102 #define OSPI_IRQ_SIG_EN 0xF8
103
104 /* Parameters */
105 #define OSPI_NUM_CS 4
106 #define OSPI_DUMMY_CYCLE_MAX 255
107 #define OSPI_WAIT_MAX_MSEC 100
108
109 struct f_ospi {
110 void __iomem *base;
111 struct udevice *dev;
112 struct clk clk;
113
114 u32 mode;
115 u32 max_speed_hz;
116 u32 num_cs;
117 u32 chip_select;
118 };
119
f_ospi_get_dummy_cycle(const struct spi_mem_op * op)120 static u32 f_ospi_get_dummy_cycle(const struct spi_mem_op *op)
121 {
122 return (op->dummy.nbytes * 8) / op->dummy.buswidth;
123 }
124
f_ospi_clear_irq(struct f_ospi * ospi)125 static void f_ospi_clear_irq(struct f_ospi *ospi)
126 {
127 writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP,
128 ospi->base + OSPI_IRQ);
129 }
130
f_ospi_enable_irq_status(struct f_ospi * ospi,u32 irq_bits)131 static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits)
132 {
133 u32 val;
134
135 val = readl(ospi->base + OSPI_IRQ_STAT_EN);
136 val |= irq_bits;
137 writel(val, ospi->base + OSPI_IRQ_STAT_EN);
138 }
139
f_ospi_disable_irq_status(struct f_ospi * ospi,u32 irq_bits)140 static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits)
141 {
142 u32 val;
143
144 val = readl(ospi->base + OSPI_IRQ_STAT_EN);
145 val &= ~irq_bits;
146 writel(val, ospi->base + OSPI_IRQ_STAT_EN);
147 }
148
f_ospi_disable_irq_output(struct f_ospi * ospi,u32 irq_bits)149 static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits)
150 {
151 u32 val;
152
153 val = readl(ospi->base + OSPI_IRQ_SIG_EN);
154 val &= ~irq_bits;
155 writel(val, ospi->base + OSPI_IRQ_SIG_EN);
156 }
157
f_ospi_prepare_config(struct f_ospi * ospi)158 static int f_ospi_prepare_config(struct f_ospi *ospi)
159 {
160 u32 val, stat0, stat1;
161
162 /* G4: Disable internal clock */
163 val = readl(ospi->base + OSPI_CLK_CTL);
164 val &= ~(OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN);
165 writel(val, ospi->base + OSPI_CLK_CTL);
166
167 /* G5: Wait for stop */
168 stat0 = OSPI_STAT_IS_AXI_WRITING | OSPI_STAT_IS_AXI_READING;
169 stat1 = OSPI_STAT_IS_SPI_IDLE | OSPI_STAT_IS_SPI_INT_CLK_STOP;
170
171 return readl_poll_timeout(ospi->base + OSPI_STAT,
172 val, (val & (stat0 | stat1)) == stat1,
173 OSPI_WAIT_MAX_MSEC);
174 }
175
f_ospi_unprepare_config(struct f_ospi * ospi)176 static int f_ospi_unprepare_config(struct f_ospi *ospi)
177 {
178 u32 val;
179
180 /* G11: Enable internal clock */
181 val = readl(ospi->base + OSPI_CLK_CTL);
182 val |= OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN;
183 writel(val, ospi->base + OSPI_CLK_CTL);
184
185 /* G12: Wait for clock to start */
186 return readl_poll_timeout(ospi->base + OSPI_STAT,
187 val, !(val & OSPI_STAT_IS_SPI_INT_CLK_STOP),
188 OSPI_WAIT_MAX_MSEC);
189 }
190
f_ospi_config_clk(struct f_ospi * ospi,u32 device_hz)191 static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz)
192 {
193 long rate_hz = clk_get_rate(&ospi->clk);
194 u32 div = DIV_ROUND_UP(rate_hz, device_hz);
195 u32 div_reg;
196 u32 val;
197
198 if (rate_hz < device_hz) {
199 dev_warn(ospi->dev, "Device frequency too large: %d\n",
200 device_hz);
201 div_reg = OSPI_CLK_CTL_DIV_1;
202 } else {
203 if (div == 1) {
204 div_reg = OSPI_CLK_CTL_DIV_1;
205 } else if (div == 2) {
206 div_reg = OSPI_CLK_CTL_DIV_2;
207 } else if (div <= 4) {
208 div_reg = OSPI_CLK_CTL_DIV_4;
209 } else if (div <= 8) {
210 div_reg = OSPI_CLK_CTL_DIV_8;
211 } else {
212 dev_warn(ospi->dev, "Device frequency too small: %d\n",
213 device_hz);
214 div_reg = OSPI_CLK_CTL_DIV_8;
215 }
216 }
217
218 /*
219 * G7: Set clock mode
220 * clock phase is fixed at 180 degrees and configure edge direction
221 * instead.
222 */
223 val = readl(ospi->base + OSPI_CLK_CTL);
224
225 val &= ~(OSPI_CLK_CTL_PHA | OSPI_CLK_CTL_DIV);
226 val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180)
227 | FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg);
228
229 writel(val, ospi->base + OSPI_CLK_CTL);
230 }
231
f_ospi_config_dll(struct f_ospi * ospi)232 static void f_ospi_config_dll(struct f_ospi *ospi)
233 {
234 /* G8: Configure DLL, nothing */
235 }
236
f_ospi_get_mode(struct f_ospi * ospi,int width,int data_size)237 static u8 f_ospi_get_mode(struct f_ospi *ospi, int width, int data_size)
238 {
239 u8 mode = OSPI_PROT_MODE_SINGLE;
240
241 switch (width) {
242 case 1:
243 mode = OSPI_PROT_MODE_SINGLE;
244 break;
245 case 2:
246 mode = OSPI_PROT_MODE_DUAL;
247 break;
248 case 4:
249 mode = OSPI_PROT_MODE_QUAD;
250 break;
251 case 8:
252 mode = OSPI_PROT_MODE_OCTAL;
253 break;
254 default:
255 if (data_size)
256 dev_err(ospi->dev, "Invalid buswidth: %d\n", width);
257 break;
258 }
259
260 return mode;
261 }
262
f_ospi_config_indir_protocol(struct f_ospi * ospi,const struct spi_mem_op * op)263 static void f_ospi_config_indir_protocol(struct f_ospi *ospi,
264 const struct spi_mem_op *op)
265 {
266 u8 mode;
267 u32 prot = 0, val;
268 int unit;
269
270 /* Set one chip select */
271 writel(BIT(ospi->chip_select), ospi->base + OSPI_SSEL);
272
273 mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1);
274 prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode);
275
276 mode = f_ospi_get_mode(ospi, op->addr.buswidth, op->addr.nbytes);
277 prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode);
278
279 mode = f_ospi_get_mode(ospi, op->data.buswidth, op->data.nbytes);
280 prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode);
281
282 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR);
283 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR);
284 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR);
285 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR);
286
287 if (ospi->mode & SPI_LSB_FIRST)
288 prot |= OSPI_PROT_BIT_POS_DATA | OSPI_PROT_BIT_POS_ALT
289 | OSPI_PROT_BIT_POS_ADDR | OSPI_PROT_BIT_POS_CODE;
290
291 if (ospi->mode & SPI_CPHA)
292 prot |= OSPI_PROT_SAMP_EDGE;
293
294 /* Examine nbytes % 4 */
295 switch (op->data.nbytes & 0x3) {
296 case 0:
297 unit = OSPI_PROT_DATA_UNIT_4B;
298 val = 0;
299 break;
300 case 2:
301 unit = OSPI_PROT_DATA_UNIT_2B;
302 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
303 break;
304 default:
305 unit = OSPI_PROT_DATA_UNIT_1B;
306 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
307 break;
308 }
309 prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit);
310
311 switch (op->data.dir) {
312 case SPI_MEM_DATA_IN:
313 prot |= OSPI_PROT_DATA_EN;
314 break;
315
316 case SPI_MEM_DATA_OUT:
317 prot |= OSPI_PROT_TRANS_DIR_WRITE | OSPI_PROT_DATA_EN;
318 break;
319
320 case SPI_MEM_NO_DATA:
321 prot |= OSPI_PROT_TRANS_DIR_WRITE;
322 break;
323
324 default:
325 dev_warn(ospi->dev, "Unsupported direction");
326 break;
327 }
328
329 prot |= FIELD_PREP(OSPI_PROT_ADDR_SIZE_MASK, op->addr.nbytes);
330 prot |= FIELD_PREP(OSPI_PROT_CODE_SIZE_MASK, 1); /* 1byte */
331
332 writel(prot, ospi->base + OSPI_PROT_CTL_INDIR);
333 writel(val, ospi->base + OSPI_DAT_SIZE_INDIR);
334 }
335
f_ospi_indir_prepare_op(struct f_ospi * ospi,const struct spi_mem_op * op)336 static int f_ospi_indir_prepare_op(struct f_ospi *ospi,
337 const struct spi_mem_op *op)
338 {
339 u32 irq_stat_en;
340 int ret;
341
342 ret = f_ospi_prepare_config(ospi);
343 if (ret)
344 return ret;
345
346 f_ospi_config_clk(ospi, ospi->max_speed_hz);
347
348 f_ospi_config_indir_protocol(ospi, op);
349
350 writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR);
351 writel(op->addr.val, ospi->base + OSPI_ADDR);
352 writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR);
353
354 f_ospi_clear_irq(ospi);
355
356 switch (op->data.dir) {
357 case SPI_MEM_DATA_IN:
358 irq_stat_en = OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
359 break;
360
361 case SPI_MEM_DATA_OUT:
362 irq_stat_en = OSPI_IRQ_WRITE_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
363 break;
364
365 case SPI_MEM_NO_DATA:
366 irq_stat_en = OSPI_IRQ_CS_TRANS_COMP;
367 break;
368
369 default:
370 dev_warn(ospi->dev, "Unsupported direction");
371 irq_stat_en = 0;
372 }
373
374 f_ospi_disable_irq_status(ospi, ~irq_stat_en);
375 f_ospi_enable_irq_status(ospi, irq_stat_en);
376
377 return f_ospi_unprepare_config(ospi);
378 }
379
f_ospi_indir_start_xfer(struct f_ospi * ospi)380 static void f_ospi_indir_start_xfer(struct f_ospi *ospi)
381 {
382 /* Write only 1, auto cleared */
383 writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL);
384 }
385
f_ospi_indir_stop_xfer(struct f_ospi * ospi)386 static void f_ospi_indir_stop_xfer(struct f_ospi *ospi)
387 {
388 /* Write only 1, auto cleared */
389 writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL);
390 }
391
f_ospi_indir_wait_xfer_complete(struct f_ospi * ospi)392 static int f_ospi_indir_wait_xfer_complete(struct f_ospi *ospi)
393 {
394 u32 val;
395
396 return readl_poll_timeout(ospi->base + OSPI_IRQ, val,
397 val & OSPI_IRQ_CS_TRANS_COMP,
398 OSPI_WAIT_MAX_MSEC);
399 }
400
f_ospi_indir_read(struct f_ospi * ospi,const struct spi_mem_op * op)401 static int f_ospi_indir_read(struct f_ospi *ospi,
402 const struct spi_mem_op *op)
403 {
404 u8 *buf = op->data.buf.in;
405 u32 val;
406 int i, ret;
407
408 /* E1-2: Prepare transfer operation */
409 ret = f_ospi_indir_prepare_op(ospi, op);
410 if (ret)
411 goto out;
412
413 f_ospi_indir_start_xfer(ospi);
414
415 /* E3-4: Wait for ready and read data */
416 for (i = 0; i < op->data.nbytes; i++) {
417 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
418 val & OSPI_IRQ_READ_BUF_READY,
419 OSPI_WAIT_MAX_MSEC);
420 if (ret)
421 goto out;
422
423 buf[i] = readl(ospi->base + OSPI_DAT) & 0xFF;
424 }
425
426 /* E5-6: Stop transfer if data size is nothing */
427 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
428 f_ospi_indir_stop_xfer(ospi);
429
430 /* E7-8: Wait for completion and clear */
431 ret = f_ospi_indir_wait_xfer_complete(ospi);
432 if (ret)
433 goto out;
434
435 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
436
437 /* E9: Do nothing if data size is valid */
438 if (readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)
439 goto out;
440
441 /* E10-11: Reset and check read fifo */
442 writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST);
443
444 ret = readl_poll_timeout(ospi->base + OSPI_SWRST, val,
445 !(val & OSPI_SWRST_INDIR_READ_FIFO),
446 OSPI_WAIT_MAX_MSEC);
447 out:
448 return ret;
449 }
450
f_ospi_indir_write(struct f_ospi * ospi,const struct spi_mem_op * op)451 static int f_ospi_indir_write(struct f_ospi *ospi,
452 const struct spi_mem_op *op)
453 {
454 u8 *buf = (u8 *)op->data.buf.out;
455 u32 val;
456 int i, ret;
457
458 /* F1-3: Prepare transfer operation */
459 ret = f_ospi_indir_prepare_op(ospi, op);
460 if (ret)
461 goto out;
462
463 f_ospi_indir_start_xfer(ospi);
464
465 if (!(readl(ospi->base + OSPI_PROT_CTL_INDIR) & OSPI_PROT_DATA_EN))
466 goto nodata;
467
468 /* F4-5: Wait for buffer ready and write data */
469 for (i = 0; i < op->data.nbytes; i++) {
470 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
471 val & OSPI_IRQ_WRITE_BUF_READY,
472 OSPI_WAIT_MAX_MSEC);
473 if (ret)
474 goto out;
475
476 writel(buf[i], ospi->base + OSPI_DAT);
477 }
478
479 /* F6-7: Stop transfer if data size is nothing */
480 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
481 f_ospi_indir_stop_xfer(ospi);
482
483 nodata:
484 /* F8-9: Wait for completion and clear */
485 ret = f_ospi_indir_wait_xfer_complete(ospi);
486 if (ret)
487 goto out;
488
489 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
490 out:
491 return ret;
492 }
493
f_ospi_exec_op(struct spi_slave * slave,const struct spi_mem_op * op)494 static int f_ospi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
495 {
496 struct f_ospi *ospi = dev_get_priv(slave->dev->parent);
497 struct dm_spi_slave_plat *slave_plat;
498 int err = 0;
499
500 slave_plat = dev_get_parent_plat(slave->dev);
501 ospi->chip_select = slave_plat->cs;
502
503 switch (op->data.dir) {
504 case SPI_MEM_DATA_IN:
505 err = f_ospi_indir_read(ospi, op);
506 break;
507
508 case SPI_MEM_DATA_OUT:
509 fallthrough;
510 case SPI_MEM_NO_DATA:
511 err = f_ospi_indir_write(ospi, op);
512 break;
513
514 default:
515 dev_warn(ospi->dev, "Unsupported direction");
516 err = -EOPNOTSUPP;
517 }
518
519 return err;
520 }
521
f_ospi_supports_op_width(const struct spi_mem_op * op)522 static bool f_ospi_supports_op_width(const struct spi_mem_op *op)
523 {
524 u8 width_available[] = { 0, 1, 2, 4, 8 };
525 u8 width_op[] = { op->cmd.buswidth, op->addr.buswidth,
526 op->dummy.buswidth, op->data.buswidth };
527 bool is_match_found;
528 int i, j;
529
530 for (i = 0; i < ARRAY_SIZE(width_op); i++) {
531 is_match_found = false;
532
533 for (j = 0; j < ARRAY_SIZE(width_available); j++) {
534 if (width_op[i] == width_available[j]) {
535 is_match_found = true;
536 break;
537 }
538 }
539
540 if (!is_match_found)
541 return false;
542 }
543
544 return true;
545 }
546
f_ospi_supports_op(struct spi_slave * slave,const struct spi_mem_op * op)547 static bool f_ospi_supports_op(struct spi_slave *slave,
548 const struct spi_mem_op *op)
549 {
550 if (f_ospi_get_dummy_cycle(op) > OSPI_DUMMY_CYCLE_MAX)
551 return false;
552
553 if (op->addr.nbytes > 4)
554 return false;
555
556 if (!f_ospi_supports_op_width(op))
557 return false;
558
559 return spi_mem_default_supports_op(slave, op);
560 }
561
f_ospi_adjust_op_size(struct spi_slave * slave,struct spi_mem_op * op)562 static int f_ospi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
563 {
564 op->data.nbytes = min((int)op->data.nbytes, (int)(OSPI_DAT_SIZE_MAX));
565
566 return 0;
567 }
568
569 static const struct spi_controller_mem_ops f_ospi_mem_ops = {
570 .adjust_op_size = f_ospi_adjust_op_size,
571 .supports_op = f_ospi_supports_op,
572 .exec_op = f_ospi_exec_op,
573 };
574
f_ospi_set_speed(struct udevice * bus,u32 speed)575 static int f_ospi_set_speed(struct udevice *bus, u32 speed)
576 {
577 struct f_ospi *ospi = dev_get_priv(bus);
578
579 ospi->max_speed_hz = speed;
580
581 return 0;
582 }
583
f_ospi_set_mode(struct udevice * bus,u32 mode)584 static int f_ospi_set_mode(struct udevice *bus, u32 mode)
585 {
586 struct f_ospi *ospi = dev_get_priv(bus);
587
588 ospi->mode = mode;
589
590 return 0;
591 }
592
f_ospi_init(struct f_ospi * ospi)593 static int f_ospi_init(struct f_ospi *ospi)
594 {
595 int ret;
596
597 ret = f_ospi_prepare_config(ospi);
598 if (ret)
599 return ret;
600
601 /* Disable boot signal */
602 writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE);
603
604 f_ospi_config_dll(ospi);
605
606 /* Disable IRQ */
607 f_ospi_clear_irq(ospi);
608 f_ospi_disable_irq_status(ospi, OSPI_IRQ_ALL);
609 f_ospi_disable_irq_output(ospi, OSPI_IRQ_ALL);
610
611 return f_ospi_unprepare_config(ospi);
612 }
613
f_ospi_of_to_plat(struct udevice * dev)614 static int f_ospi_of_to_plat(struct udevice *dev)
615 {
616 struct f_ospi *ospi = dev_get_priv(dev);
617
618 ospi->base = dev_read_addr_ptr(dev);
619 ospi->num_cs = dev_read_u32_default(dev, "num-cs", OSPI_NUM_CS);
620
621 return 0;
622 }
623
f_ospi_probe(struct udevice * dev)624 static int f_ospi_probe(struct udevice *dev)
625 {
626 struct f_ospi *ospi = dev_get_priv(dev);
627 int ret;
628
629 ospi->dev = dev;
630
631 ret = clk_get_by_index(dev, 0, &ospi->clk);
632 if (ret < 0) {
633 dev_err(dev, "Failed to get clock\n");
634 goto err_put_ctlr;
635 }
636
637 ret = clk_enable(&ospi->clk);
638 if (ret) {
639 dev_err(dev, "Failed to enable the clock\n");
640 goto err_put_ctlr;
641 }
642
643 ret = f_ospi_init(ospi);
644 if (ret)
645 goto err_disable_clk;
646
647 return 0;
648
649 err_disable_clk:
650 clk_disable(&ospi->clk);
651
652 err_put_ctlr:
653 dev_err(dev, "Socionext F_OSPI probe failed\n");
654 return ret;
655 }
656
f_ospi_remove(struct udevice * dev)657 static int f_ospi_remove(struct udevice *dev)
658 {
659 struct f_ospi *ospi = dev_get_priv(dev);
660
661 clk_disable(&ospi->clk);
662
663 return 0;
664 }
665
666 static const struct dm_spi_ops f_ospi_ops = {
667 .set_speed = f_ospi_set_speed,
668 .set_mode = f_ospi_set_mode,
669 .mem_ops = &f_ospi_mem_ops,
670 };
671
672 static const struct udevice_id f_ospi_dt_ids[] = {
673 { .compatible = "socionext,f-ospi" },
674 {}
675 };
676
677 U_BOOT_DRIVER(f_ospi) = {
678 .name = "sn-f-ospi",
679 .id = UCLASS_SPI,
680 .of_match = f_ospi_dt_ids,
681 .of_to_plat = f_ospi_of_to_plat,
682 .ops = &f_ospi_ops,
683 .probe = f_ospi_probe,
684 .remove = f_ospi_remove,
685 .priv_auto = sizeof(struct f_ospi),
686 };
687