1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Microchip Corporation
4 *
5 * Author: Clément Léger <clement.leger@bootlin.com>
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <timer.h>
12 #include <asm/io.h>
13 #include <linux/bitops.h>
14
15 #define TCB_CHAN(chan) ((chan) * 0x40)
16
17 #define TCB_CCR(chan) (0x0 + TCB_CHAN(chan))
18 #define TCB_CCR_CLKEN (1 << 0)
19
20 #define TCB_CMR(chan) (0x4 + TCB_CHAN(chan))
21 #define TCB_CMR_WAVE (1 << 15)
22 #define TCB_CMR_TIMER_CLOCK2 1
23 #define TCB_CMR_XC1 6
24 #define TCB_CMR_ACPA_SET (1 << 16)
25 #define TCB_CMR_ACPC_CLEAR (2 << 18)
26
27 #define TCB_CV(chan) (0x10 + TCB_CHAN(chan))
28
29 #define TCB_RA(chan) (0x14 + TCB_CHAN(chan))
30 #define TCB_RC(chan) (0x1c + TCB_CHAN(chan))
31
32 #define TCB_IDR(chan) (0x28 + TCB_CHAN(chan))
33
34 #define TCB_BCR 0xc0
35 #define TCB_BCR_SYNC (1 << 0)
36
37 #define TCB_BMR 0xc4
38 #define TCB_BMR_TC1XC1S_TIOA0 (2 << 2)
39
40 #define TCB_WPMR 0xe4
41 #define TCB_WPMR_WAKEY 0x54494d
42
43 #define TCB_CLK_DIVISOR 8
44 struct atmel_tcb_plat {
45 void __iomem *base;
46 };
47
atmel_tcb_get_count(struct udevice * dev)48 static u64 atmel_tcb_get_count(struct udevice *dev)
49 {
50 struct atmel_tcb_plat *plat = dev_get_plat(dev);
51 u64 cv0 = 0;
52 u64 cv1 = 0;
53
54 do {
55 cv1 = readl(plat->base + TCB_CV(1));
56 cv0 = readl(plat->base + TCB_CV(0));
57 } while (readl(plat->base + TCB_CV(1)) != cv1);
58
59 cv0 |= cv1 << 32;
60
61 return cv0;
62 }
63
atmel_tcb_configure(void __iomem * base)64 static void atmel_tcb_configure(void __iomem *base)
65 {
66 /* Disable write protection */
67 writel(TCB_WPMR_WAKEY, base + TCB_WPMR);
68
69 /* Disable all irqs for both channel 0 & 1 */
70 writel(0xff, base + TCB_IDR(0));
71 writel(0xff, base + TCB_IDR(1));
72
73 /*
74 * In order to avoid wrapping, use a 64 bit counter by chaining
75 * two channels.
76 * Channel 0 is configured to generate a clock on TIOA0 which is cleared
77 * when reaching 0x80000000 and set when reaching 0.
78 */
79 writel(TCB_CMR_TIMER_CLOCK2 | TCB_CMR_WAVE | TCB_CMR_ACPA_SET
80 | TCB_CMR_ACPC_CLEAR, base + TCB_CMR(0));
81 writel(0x80000000, base + TCB_RC(0));
82 writel(0x1, base + TCB_RA(0));
83 writel(TCB_CCR_CLKEN, base + TCB_CCR(0));
84
85 /* Channel 1 is configured to use TIOA0 as input */
86 writel(TCB_CMR_XC1 | TCB_CMR_WAVE, base + TCB_CMR(1));
87 writel(TCB_CCR_CLKEN, base + TCB_CCR(1));
88
89 /* Set XC1 input to be TIOA0 (ie output of Channel 0) */
90 writel(TCB_BMR_TC1XC1S_TIOA0, base + TCB_BMR);
91
92 /* Sync & start all timers */
93 writel(TCB_BCR_SYNC, base + TCB_BCR);
94 }
95
atmel_tcb_probe(struct udevice * dev)96 static int atmel_tcb_probe(struct udevice *dev)
97 {
98 struct atmel_tcb_plat *plat = dev_get_plat(dev);
99 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
100 struct clk clk;
101 ulong clk_rate;
102 int ret;
103
104 if (!device_is_compatible(dev->parent, "atmel,sama5d2-tcb"))
105 return -EINVAL;
106
107 /* Currently, we only support channel 0 and 1 to be chained */
108 if (dev_read_addr_index(dev, 0) != 0 &&
109 dev_read_addr_index(dev, 1) != 1) {
110 printf("Error: only chained timers 0 and 1 are supported\n");
111 return -EINVAL;
112 }
113
114 ret = clk_get_by_name(dev->parent, "t0_clk", &clk);
115 if (ret)
116 return -EINVAL;
117
118 ret = clk_enable(&clk);
119 if (ret)
120 return ret;
121
122 clk_rate = clk_get_rate(&clk);
123 if (!clk_rate) {
124 clk_disable(&clk);
125 return -EINVAL;
126 }
127
128 uc_priv->clock_rate = clk_rate / TCB_CLK_DIVISOR;
129
130 atmel_tcb_configure(plat->base);
131
132 return 0;
133 }
134
atmel_tcb_of_to_plat(struct udevice * dev)135 static int atmel_tcb_of_to_plat(struct udevice *dev)
136 {
137 struct atmel_tcb_plat *plat = dev_get_plat(dev);
138
139 plat->base = dev_read_addr_ptr(dev->parent);
140
141 return 0;
142 }
143
144 static const struct timer_ops atmel_tcb_ops = {
145 .get_count = atmel_tcb_get_count,
146 };
147
148 static const struct udevice_id atmel_tcb_ids[] = {
149 { .compatible = "atmel,tcb-timer" },
150 { }
151 };
152
153 U_BOOT_DRIVER(atmel_tcb) = {
154 .name = "atmel_tcb",
155 .id = UCLASS_TIMER,
156 .of_match = atmel_tcb_ids,
157 .of_to_plat = atmel_tcb_of_to_plat,
158 .plat_auto = sizeof(struct atmel_tcb_plat),
159 .probe = atmel_tcb_probe,
160 .ops = &atmel_tcb_ops,
161 };
162