1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale i.MX28 USB Host driver
4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/imx-regs.h>
12 #include <errno.h>
13 #include <linux/delay.h>
14 #include <dm.h>
15 #include <power/regulator.h>
16
17 #include "ehci.h"
18
19 /* This DIGCTL register ungates clock to USB */
20 #define HW_DIGCTL_CTRL 0x8001c000
21 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
22 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
23
24 struct ehci_mxs_port {
25 uint32_t usb_regs;
26 struct mxs_usbphy_regs *phy_regs;
27
28 struct mxs_register_32 *pll;
29 uint32_t pll_en_bits;
30 uint32_t pll_dis_bits;
31 uint32_t gate_bits;
32 };
33
ehci_mxs_toggle_clock(const struct ehci_mxs_port * port,int enable)34 static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
35 {
36 struct mxs_register_32 *digctl_ctrl =
37 (struct mxs_register_32 *)HW_DIGCTL_CTRL;
38 int pll_offset, dig_offset;
39
40 if (enable) {
41 pll_offset = offsetof(struct mxs_register_32, reg_set);
42 dig_offset = offsetof(struct mxs_register_32, reg_clr);
43 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
44 writel(port->pll_en_bits, (u32)port->pll + pll_offset);
45 } else {
46 pll_offset = offsetof(struct mxs_register_32, reg_clr);
47 dig_offset = offsetof(struct mxs_register_32, reg_set);
48 writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
49 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
50 }
51
52 return 0;
53 }
54
__ehci_hcd_init(struct ehci_mxs_port * port,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)55 static int __ehci_hcd_init(struct ehci_mxs_port *port, enum usb_init_type init,
56 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
57 {
58 u32 usb_base, cap_base;
59 int ret;
60
61 /* Reset the PHY block */
62 writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
63 udelay(10);
64 writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
65 &port->phy_regs->hw_usbphy_ctrl_clr);
66
67 /* Enable USB clock */
68 ret = ehci_mxs_toggle_clock(port, 1);
69 if (ret)
70 return ret;
71
72 /* Start USB PHY */
73 writel(0, &port->phy_regs->hw_usbphy_pwd);
74
75 /* Enable UTMI+ Level 2 and Level 3 compatibility */
76 writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
77 &port->phy_regs->hw_usbphy_ctrl_set);
78
79 usb_base = port->usb_regs + 0x100;
80 *hccr = (struct ehci_hccr *)usb_base;
81
82 cap_base = ehci_readl(&(*hccr)->cr_capbase);
83 *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
84
85 return 0;
86 }
87
__ehci_hcd_stop(struct ehci_mxs_port * port)88 static int __ehci_hcd_stop(struct ehci_mxs_port *port)
89 {
90 u32 usb_base, cap_base, tmp;
91 struct ehci_hccr *hccr;
92 struct ehci_hcor *hcor;
93
94 /* Stop the USB port */
95 usb_base = port->usb_regs + 0x100;
96 hccr = (struct ehci_hccr *)usb_base;
97 cap_base = ehci_readl(&hccr->cr_capbase);
98 hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
99
100 tmp = ehci_readl(&hcor->or_usbcmd);
101 tmp &= ~CMD_RUN;
102 ehci_writel(&hcor->or_usbcmd, tmp);
103
104 /* Disable the PHY */
105 tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
106 USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
107 USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
108 USBPHY_PWD_TXPWDFS;
109 writel(tmp, &port->phy_regs->hw_usbphy_pwd);
110
111 /* Disable USB clock */
112 return ehci_mxs_toggle_clock(port, 0);
113 }
114
115 struct ehci_mxs_priv_data {
116 struct ehci_ctrl ctrl;
117 struct usb_ehci *ehci;
118 struct udevice *vbus_supply;
119 struct ehci_mxs_port port;
120 enum usb_init_type init_type;
121 };
122
123 /*
124 * Below defines correspond to imx28 clk Linux (v5.15.y)
125 * clock driver to provide proper offset for PHY[01]
126 * devices.
127 */
128 #define CLK_USB_PHY0 62
129 #define CLK_USB_PHY1 63
130 #define PLL0CTRL0(base) ((base) + 0x0000)
131 #define PLL1CTRL0(base) ((base) + 0x0020)
132
ehci_usb_ofdata_to_platdata(struct udevice * dev)133 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
134 {
135 struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
136 struct usb_plat *plat = dev_get_plat(dev);
137 struct ehci_mxs_port *port = &priv->port;
138 u32 phandle, phy_reg, clk_reg, clk_id;
139 ofnode phy_node, clk_node;
140 const char *mode;
141 int ret;
142
143 mode = ofnode_read_string(dev->node_, "dr_mode");
144 if (mode) {
145 if (strcmp(mode, "peripheral") == 0)
146 plat->init_type = USB_INIT_DEVICE;
147 else if (strcmp(mode, "host") == 0)
148 plat->init_type = USB_INIT_HOST;
149 else
150 return -EINVAL;
151 }
152
153 /* Read base address of the USB IP block */
154 ret = ofnode_read_u32(dev->node_, "reg", &port->usb_regs);
155 if (ret)
156 return ret;
157
158 /* Read base address of the USB PHY IP block */
159 ret = ofnode_read_u32(dev->node_, "fsl,usbphy", &phandle);
160 if (ret)
161 return ret;
162
163 phy_node = ofnode_get_by_phandle(phandle);
164 if (!ofnode_valid(phy_node))
165 return -ENODEV;
166
167 ret = ofnode_read_u32(phy_node, "reg", &phy_reg);
168 if (ret)
169 return ret;
170
171 port->phy_regs = (struct mxs_usbphy_regs *)phy_reg;
172
173 /* Read base address of the CLK IP block and proper ID */
174 ret = ofnode_read_u32_index(phy_node, "clocks", 0, &phandle);
175 if (ret)
176 return ret;
177
178 ret = ofnode_read_u32_index(phy_node, "clocks", 1, &clk_id);
179 if (ret)
180 return ret;
181
182 clk_node = ofnode_get_by_phandle(phandle);
183 if (!ofnode_valid(clk_node))
184 return -ENODEV;
185
186 ret = ofnode_read_u32(clk_node, "reg", &clk_reg);
187 if (ret)
188 return ret;
189
190 port->pll = (struct mxs_register_32 *)clk_reg;
191
192 /* Provide proper offset for USB PHY clocks */
193 if (clk_id == CLK_USB_PHY0)
194 port->pll = PLL0CTRL0(port->pll);
195
196 if (clk_id == CLK_USB_PHY1)
197 port->pll = PLL1CTRL0(port->pll);
198
199 debug("%s: pll_reg: 0x%p clk_id: %d\n", __func__, port->pll, clk_id);
200 /*
201 * On the imx28 the values provided by CLKCTRL_PLL0* defines to are the
202 * same as ones for CLKCTRL_PLL1*. As a result the former can be used
203 * for both ports - i.e. (usb[01]).
204 */
205 port->pll_en_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS |
206 CLKCTRL_PLL0CTRL0_POWER;
207 port->pll_dis_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS;
208 port->gate_bits = HW_DIGCTL_CTRL_USB0_CLKGATE;
209
210 return 0;
211 }
212
ehci_usb_probe(struct udevice * dev)213 static int ehci_usb_probe(struct udevice *dev)
214 {
215 struct usb_plat *plat = dev_get_plat(dev);
216 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
217 struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
218 struct ehci_mxs_port *port = &priv->port;
219 enum usb_init_type type = plat->init_type;
220 struct ehci_hccr *hccr;
221 struct ehci_hcor *hcor;
222 int ret;
223
224 priv->ehci = ehci;
225 priv->init_type = type;
226
227 debug("%s: USB type: %s reg: 0x%x phy_reg 0x%p\n", __func__,
228 type == USB_INIT_HOST ? "HOST" : "DEVICE", port->usb_regs,
229 (uint32_t *)port->phy_regs);
230
231 #if CONFIG_IS_ENABLED(DM_REGULATOR)
232 ret = device_get_supply_regulator(dev, "vbus-supply",
233 &priv->vbus_supply);
234 if (ret)
235 debug("%s: No vbus supply\n", dev->name);
236
237 if (!ret && priv->vbus_supply) {
238 ret = regulator_set_enable(priv->vbus_supply,
239 (type == USB_INIT_DEVICE) ?
240 false : true);
241 if (ret) {
242 puts("Error enabling VBUS supply\n");
243 return ret;
244 }
245 }
246 #endif
247 ret = __ehci_hcd_init(port, type, &hccr, &hcor);
248 if (ret)
249 return ret;
250
251 mdelay(10);
252 return ehci_register(dev, hccr, hcor, NULL, 0, priv->init_type);
253 }
254
ehci_usb_remove(struct udevice * dev)255 static int ehci_usb_remove(struct udevice *dev)
256 {
257 struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
258 struct ehci_mxs_port *port = &priv->port;
259 int ret;
260
261 ret = ehci_deregister(dev);
262 if (ret)
263 return ret;
264
265 #if CONFIG_IS_ENABLED(DM_REGULATOR)
266 if (priv->vbus_supply) {
267 ret = regulator_set_enable(priv->vbus_supply, false);
268 if (ret) {
269 puts("Error disabling VBUS supply\n");
270 return ret;
271 }
272 }
273 #endif
274 return __ehci_hcd_stop(port);
275 }
276
277 static const struct udevice_id mxs_usb_ids[] = {
278 { .compatible = "fsl,imx28-usb" },
279 { }
280 };
281
282 U_BOOT_DRIVER(usb_mxs) = {
283 .name = "ehci_mxs",
284 .id = UCLASS_USB,
285 .of_match = mxs_usb_ids,
286 .of_to_plat = ehci_usb_ofdata_to_platdata,
287 .probe = ehci_usb_probe,
288 .remove = ehci_usb_remove,
289 .ops = &ehci_usb_ops,
290 .plat_auto = sizeof(struct usb_plat),
291 .priv_auto = sizeof(struct ehci_mxs_priv_data),
292 .flags = DM_FLAG_ALLOC_PRIV_DMA,
293 };
294