1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
4 */
5
6 #include <common.h>
7 #include <clk.h>
8 #include <display.h>
9 #include <dm.h>
10 #include <dw_hdmi.h>
11 #include <edid.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <regmap.h>
15 #include <syscon.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/hardware.h>
20 #include <asm/arch-rockchip/grf_rk3288.h>
21 #include <power/regulator.h>
22 #include "rk_hdmi.h"
23
rk3288_hdmi_enable(struct udevice * dev,int panel_bpp,const struct display_timing * edid)24 static int rk3288_hdmi_enable(struct udevice *dev, int panel_bpp,
25 const struct display_timing *edid)
26 {
27 struct rk_hdmi_priv *priv = dev_get_priv(dev);
28 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
29 int vop_id = uc_plat->source_id;
30 struct rk3288_grf *grf = priv->grf;
31
32 /* hdmi source select hdmi controller */
33 rk_setreg(&grf->soc_con6, 1 << 15);
34
35 /* hdmi data from vop id */
36 rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0);
37
38 return dw_hdmi_enable(&priv->hdmi, edid);
39 }
40
rk3288_hdmi_of_to_plat(struct udevice * dev)41 static int rk3288_hdmi_of_to_plat(struct udevice *dev)
42 {
43 struct rk_hdmi_priv *priv = dev_get_priv(dev);
44 struct dw_hdmi *hdmi = &priv->hdmi;
45
46 hdmi->i2c_clk_high = 0x7a;
47 hdmi->i2c_clk_low = 0x8d;
48
49 /*
50 * TODO(sjg@chromium.org): The above values don't work - these
51 * ones work better, but generate lots of errors in the data.
52 */
53 hdmi->i2c_clk_high = 0x0d;
54 hdmi->i2c_clk_low = 0x0d;
55
56 return rk_hdmi_of_to_plat(dev);
57 }
58
rk3288_clk_config(struct udevice * dev)59 static int rk3288_clk_config(struct udevice *dev)
60 {
61 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
62 struct clk clk;
63 int ret;
64
65 /*
66 * Configure the maximum clock to permit whatever resolution the
67 * monitor wants
68 */
69 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
70 if (ret >= 0) {
71 ret = clk_set_rate(&clk, 384000000);
72 clk_free(&clk);
73 }
74 if (ret < 0) {
75 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
76 __func__, uc_plat->src_dev->name, ret);
77 return ret;
78 }
79
80 return 0;
81 }
82
83 static const char * const rk3288_regulator_names[] = {
84 "vcc50_hdmi"
85 };
86
rk3288_hdmi_probe(struct udevice * dev)87 static int rk3288_hdmi_probe(struct udevice *dev)
88 {
89 /* Enable VOP clock for RK3288 */
90 rk3288_clk_config(dev);
91
92 /* Enable regulators required for HDMI */
93 rk_hdmi_probe_regulators(dev, rk3288_regulator_names,
94 ARRAY_SIZE(rk3288_regulator_names));
95
96 return rk_hdmi_probe(dev);
97 }
98
99 static const struct dm_display_ops rk3288_hdmi_ops = {
100 .read_edid = rk_hdmi_read_edid,
101 .enable = rk3288_hdmi_enable,
102 };
103
104 static const struct udevice_id rk3288_hdmi_ids[] = {
105 { .compatible = "rockchip,rk3288-dw-hdmi" },
106 { }
107 };
108
109 U_BOOT_DRIVER(rk3288_hdmi_rockchip) = {
110 .name = "rk3288_hdmi_rockchip",
111 .id = UCLASS_DISPLAY,
112 .of_match = rk3288_hdmi_ids,
113 .ops = &rk3288_hdmi_ops,
114 .of_to_plat = rk3288_hdmi_of_to_plat,
115 .probe = rk3288_hdmi_probe,
116 .priv_auto = sizeof(struct rk_hdmi_priv),
117 };
118