1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 NVIDIA Corporation
4 * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <log.h>
10 #include <misc.h>
11 #include <mipi_display.h>
12 #include <mipi_dsi.h>
13 #include <backlight.h>
14 #include <panel.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <power/regulator.h>
18
19 #include <asm/gpio.h>
20 #include <asm/io.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/display.h>
23 #include <asm/arch-tegra30/dsi.h>
24
25 #include "mipi-phy.h"
26
27 #define USEC_PER_SEC 1000000L
28 #define NSEC_PER_SEC 1000000000L
29
30 struct tegra_dsi_priv {
31 struct mipi_dsi_host host;
32 struct mipi_dsi_device device;
33 struct mipi_dphy_timing dphy_timing;
34
35 struct udevice *panel;
36 struct display_timing timing;
37
38 struct dsi_ctlr *dsi;
39 struct udevice *avdd;
40
41 enum tegra_dsi_format format;
42
43 int dsi_clk;
44 int video_fifo_depth;
45 int host_fifo_depth;
46 };
47
tegra_dc_enable_controller(struct udevice * dev)48 static void tegra_dc_enable_controller(struct udevice *dev)
49 {
50 struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
51 struct dc_ctlr *dc = dc_plat->dc;
52 u32 value;
53
54 value = readl(&dc->disp.disp_win_opt);
55 value |= DSI_ENABLE;
56 writel(value, &dc->disp.disp_win_opt);
57
58 writel(GENERAL_UPDATE, &dc->cmd.state_ctrl);
59 writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl);
60 }
61
62 static const char * const error_report[16] = {
63 "SoT Error",
64 "SoT Sync Error",
65 "EoT Sync Error",
66 "Escape Mode Entry Command Error",
67 "Low-Power Transmit Sync Error",
68 "Peripheral Timeout Error",
69 "False Control Error",
70 "Contention Detected",
71 "ECC Error, single-bit",
72 "ECC Error, multi-bit",
73 "Checksum Error",
74 "DSI Data Type Not Recognized",
75 "DSI VC ID Invalid",
76 "Invalid Transmission Length",
77 "Reserved",
78 "DSI Protocol Violation",
79 };
80
tegra_dsi_read_response(struct dsi_misc_reg * misc,const struct mipi_dsi_msg * msg,size_t count)81 static ssize_t tegra_dsi_read_response(struct dsi_misc_reg *misc,
82 const struct mipi_dsi_msg *msg,
83 size_t count)
84 {
85 u8 *rx = msg->rx_buf;
86 unsigned int i, j, k;
87 size_t size = 0;
88 u16 errors;
89 u32 value;
90
91 /* read and parse packet header */
92 value = readl(&misc->dsi_rd_data);
93
94 switch (value & 0x3f) {
95 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
96 errors = (value >> 8) & 0xffff;
97 printf("%s: Acknowledge and error report: %04x\n",
98 __func__, errors);
99 for (i = 0; i < ARRAY_SIZE(error_report); i++)
100 if (errors & BIT(i))
101 printf("%s: %2u: %s\n", __func__, i,
102 error_report[i]);
103 break;
104
105 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
106 rx[0] = (value >> 8) & 0xff;
107 size = 1;
108 break;
109
110 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
111 rx[0] = (value >> 8) & 0xff;
112 rx[1] = (value >> 16) & 0xff;
113 size = 2;
114 break;
115
116 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
117 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
118 break;
119
120 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
121 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
122 break;
123
124 default:
125 printf("%s: unhandled response type: %02x\n",
126 __func__, value & 0x3f);
127 return -EPROTO;
128 }
129
130 size = min(size, msg->rx_len);
131
132 if (msg->rx_buf && size > 0) {
133 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
134 u8 *rx = msg->rx_buf + j;
135
136 value = readl(&misc->dsi_rd_data);
137
138 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
139 rx[j + k] = (value >> (k << 3)) & 0xff;
140 }
141 }
142
143 return size;
144 }
145
tegra_dsi_transmit(struct dsi_misc_reg * misc,unsigned long timeout)146 static int tegra_dsi_transmit(struct dsi_misc_reg *misc,
147 unsigned long timeout)
148 {
149 writel(DSI_TRIGGER_HOST, &misc->dsi_trigger);
150
151 while (timeout--) {
152 u32 value = readl(&misc->dsi_trigger);
153
154 if ((value & DSI_TRIGGER_HOST) == 0)
155 return 0;
156
157 udelay(1000);
158 }
159
160 debug("timeout waiting for transmission to complete\n");
161 return -ETIMEDOUT;
162 }
163
tegra_dsi_wait_for_response(struct dsi_misc_reg * misc,unsigned long timeout)164 static int tegra_dsi_wait_for_response(struct dsi_misc_reg *misc,
165 unsigned long timeout)
166 {
167 while (timeout--) {
168 u32 value = readl(&misc->dsi_status);
169 u8 count = value & 0x1f;
170
171 if (count > 0)
172 return count;
173
174 udelay(1000);
175 }
176
177 debug("peripheral returned no data\n");
178 return -ETIMEDOUT;
179 }
180
tegra_dsi_writesl(struct dsi_misc_reg * misc,const void * buffer,size_t size)181 static void tegra_dsi_writesl(struct dsi_misc_reg *misc,
182 const void *buffer, size_t size)
183 {
184 const u8 *buf = buffer;
185 size_t i, j;
186 u32 value;
187
188 for (j = 0; j < size; j += 4) {
189 value = 0;
190
191 for (i = 0; i < 4 && j + i < size; i++)
192 value |= buf[j + i] << (i << 3);
193
194 writel(value, &misc->dsi_wr_data);
195 }
196 }
197
tegra_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)198 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
199 const struct mipi_dsi_msg *msg)
200 {
201 struct udevice *dev = (struct udevice *)host->dev;
202 struct tegra_dsi_priv *priv = dev_get_priv(dev);
203 struct dsi_misc_reg *misc = &priv->dsi->misc;
204 struct mipi_dsi_packet packet;
205 const u8 *header;
206 size_t count;
207 ssize_t err;
208 u32 value;
209
210 err = mipi_dsi_create_packet(&packet, msg);
211 if (err < 0)
212 return err;
213
214 header = packet.header;
215
216 /* maximum FIFO depth is 1920 words */
217 if (packet.size > priv->video_fifo_depth * 4)
218 return -ENOSPC;
219
220 /* reset underflow/overflow flags */
221 value = readl(&misc->dsi_status);
222 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
223 value = DSI_HOST_CONTROL_FIFO_RESET;
224 writel(value, &misc->host_dsi_ctrl);
225 udelay(10);
226 }
227
228 value = readl(&misc->dsi_pwr_ctrl);
229 value |= DSI_POWER_CONTROL_ENABLE;
230 writel(value, &misc->dsi_pwr_ctrl);
231
232 mdelay(5);
233
234 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
235 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
236
237 /*
238 * The host FIFO has a maximum of 64 words, so larger transmissions
239 * need to use the video FIFO.
240 */
241 if (packet.size > priv->host_fifo_depth * 4)
242 value |= DSI_HOST_CONTROL_FIFO_SEL;
243
244 writel(value, &misc->host_dsi_ctrl);
245
246 /*
247 * For reads and messages with explicitly requested ACK, generate a
248 * BTA sequence after the transmission of the packet.
249 */
250 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
251 (msg->rx_buf && msg->rx_len > 0)) {
252 value = readl(&misc->host_dsi_ctrl);
253 value |= DSI_HOST_CONTROL_PKT_BTA;
254 writel(value, &misc->host_dsi_ctrl);
255 }
256
257 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
258 writel(value, &misc->dsi_ctrl);
259
260 /* write packet header, ECC is generated by hardware */
261 value = header[2] << 16 | header[1] << 8 | header[0];
262 writel(value, &misc->dsi_wr_data);
263
264 /* write payload (if any) */
265 if (packet.payload_length > 0)
266 tegra_dsi_writesl(misc, packet.payload,
267 packet.payload_length);
268
269 err = tegra_dsi_transmit(misc, 250);
270 if (err < 0)
271 return err;
272
273 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
274 (msg->rx_buf && msg->rx_len > 0)) {
275 err = tegra_dsi_wait_for_response(misc, 250);
276 if (err < 0)
277 return err;
278
279 count = err;
280
281 value = readl(&misc->dsi_rd_data);
282 switch (value) {
283 case 0x84:
284 debug("%s: ACK\n", __func__);
285 break;
286
287 case 0x87:
288 debug("%s: ESCAPE\n", __func__);
289 break;
290
291 default:
292 printf("%s: unknown status: %08x\n", __func__, value);
293 break;
294 }
295
296 if (count > 1) {
297 err = tegra_dsi_read_response(misc, msg, count);
298 if (err < 0) {
299 printf("%s: failed to parse response: %zd\n",
300 __func__, err);
301 } else {
302 /*
303 * For read commands, return the number of
304 * bytes returned by the peripheral.
305 */
306 count = err;
307 }
308 }
309 } else {
310 /*
311 * For write commands, we have transmitted the 4-byte header
312 * plus the variable-length payload.
313 */
314 count = 4 + packet.payload_length;
315 }
316
317 return count;
318 }
319
320 struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = {
321 .transfer = tegra_dsi_host_transfer,
322 };
323
324 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
325 #define PKT_LEN0(len) (((len) & 0x07) << 0)
326 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
327 #define PKT_LEN1(len) (((len) & 0x07) << 10)
328 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
329 #define PKT_LEN2(len) (((len) & 0x07) << 20)
330
331 #define PKT_LP BIT(30)
332 #define NUM_PKT_SEQ 12
333
334 /*
335 * non-burst mode with sync pulses
336 */
337 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
338 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
339 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
340 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
341 PKT_LP,
342 [ 1] = 0,
343 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
344 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
345 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
346 PKT_LP,
347 [ 3] = 0,
348 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
349 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
350 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
351 PKT_LP,
352 [ 5] = 0,
353 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
354 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
355 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
356 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
357 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
358 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
359 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
360 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
361 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
362 PKT_LP,
363 [ 9] = 0,
364 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
365 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
366 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
367 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
368 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
369 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
370 };
371
372 /*
373 * non-burst mode with sync events
374 */
375 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
376 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
377 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
378 PKT_LP,
379 [ 1] = 0,
380 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
381 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
382 PKT_LP,
383 [ 3] = 0,
384 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
385 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
386 PKT_LP,
387 [ 5] = 0,
388 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
389 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
390 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
391 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
392 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
393 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
394 PKT_LP,
395 [ 9] = 0,
396 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
397 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
398 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
399 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
400 };
401
402 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
403 [ 0] = 0,
404 [ 1] = 0,
405 [ 2] = 0,
406 [ 3] = 0,
407 [ 4] = 0,
408 [ 5] = 0,
409 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
410 [ 7] = 0,
411 [ 8] = 0,
412 [ 9] = 0,
413 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
414 [11] = 0,
415 };
416
tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,unsigned int * mulp,unsigned int * divp)417 static void tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
418 unsigned int *mulp, unsigned int *divp)
419 {
420 switch (format) {
421 case MIPI_DSI_FMT_RGB666_PACKED:
422 case MIPI_DSI_FMT_RGB888:
423 *mulp = 3;
424 *divp = 1;
425 break;
426
427 case MIPI_DSI_FMT_RGB565:
428 *mulp = 2;
429 *divp = 1;
430 break;
431
432 case MIPI_DSI_FMT_RGB666:
433 *mulp = 9;
434 *divp = 4;
435 break;
436
437 default:
438 break;
439 }
440 }
441
tegra_dsi_get_format(enum mipi_dsi_pixel_format format,enum tegra_dsi_format * fmt)442 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
443 enum tegra_dsi_format *fmt)
444 {
445 switch (format) {
446 case MIPI_DSI_FMT_RGB888:
447 *fmt = TEGRA_DSI_FORMAT_24P;
448 break;
449
450 case MIPI_DSI_FMT_RGB666:
451 *fmt = TEGRA_DSI_FORMAT_18NP;
452 break;
453
454 case MIPI_DSI_FMT_RGB666_PACKED:
455 *fmt = TEGRA_DSI_FORMAT_18P;
456 break;
457
458 case MIPI_DSI_FMT_RGB565:
459 *fmt = TEGRA_DSI_FORMAT_16P;
460 break;
461
462 default:
463 return -EINVAL;
464 }
465
466 return 0;
467 }
468
tegra_dsi_pad_calibrate(struct dsi_pad_ctrl_reg * pad)469 static void tegra_dsi_pad_calibrate(struct dsi_pad_ctrl_reg *pad)
470 {
471 u32 value;
472
473 /* start calibration */
474 value = DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
475 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
476 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
477 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
478 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6) |
479 DSI_PAD_CONTROL_PAD_PDIO(0) |
480 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
481 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0);
482 writel(value, &pad->pad_ctrl);
483
484 clock_enable(PERIPH_ID_VI);
485 clock_enable(PERIPH_ID_CSI);
486 udelay(2);
487 reset_set_enable(PERIPH_ID_VI, 0);
488 reset_set_enable(PERIPH_ID_CSI, 0);
489
490 value = MIPI_CAL_TERMOSA(0x4);
491 writel(value, TEGRA_VI_BASE + (CSI_CILA_MIPI_CAL_CONFIG_0 << 2));
492
493 value = MIPI_CAL_TERMOSB(0x4);
494 writel(value, TEGRA_VI_BASE + (CSI_CILB_MIPI_CAL_CONFIG_0 << 2));
495
496 value = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
497 writel(value, TEGRA_VI_BASE + (CSI_DSI_MIPI_CAL_CONFIG << 2));
498
499 value = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
500 writel(value, TEGRA_VI_BASE + (CSI_MIPIBIAS_PAD_CONFIG << 2));
501
502 value = PAD_CIL_PDVREG(0x0);
503 writel(value, TEGRA_VI_BASE + (CSI_CIL_PAD_CONFIG << 2));
504 }
505
tegra_dsi_set_timeout(struct dsi_timeout_reg * rtimeout,unsigned long bclk,unsigned int vrefresh)506 static void tegra_dsi_set_timeout(struct dsi_timeout_reg *rtimeout,
507 unsigned long bclk,
508 unsigned int vrefresh)
509 {
510 unsigned int timeout;
511 u32 value;
512
513 /* one frame high-speed transmission timeout */
514 timeout = (bclk / vrefresh) / 512;
515 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
516 writel(value, &rtimeout->dsi_timeout_0);
517
518 /* 2 ms peripheral timeout for panel */
519 timeout = 2 * bclk / 512 * 1000;
520 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
521 writel(value, &rtimeout->dsi_timeout_1);
522
523 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
524 writel(value, &rtimeout->dsi_to_tally);
525 }
526
tegra_dsi_set_phy_timing(struct dsi_timing_reg * ptiming,unsigned long period,const struct mipi_dphy_timing * dphy_timing)527 static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming,
528 unsigned long period,
529 const struct mipi_dphy_timing *dphy_timing)
530 {
531 u32 value;
532
533 value = DSI_TIMING_FIELD(dphy_timing->hsexit, period, 1) << 24 |
534 DSI_TIMING_FIELD(dphy_timing->hstrail, period, 0) << 16 |
535 DSI_TIMING_FIELD(dphy_timing->hszero, period, 3) << 8 |
536 DSI_TIMING_FIELD(dphy_timing->hsprepare, period, 1);
537 writel(value, &ptiming->dsi_phy_timing_0);
538
539 value = DSI_TIMING_FIELD(dphy_timing->clktrail, period, 1) << 24 |
540 DSI_TIMING_FIELD(dphy_timing->clkpost, period, 1) << 16 |
541 DSI_TIMING_FIELD(dphy_timing->clkzero, period, 1) << 8 |
542 DSI_TIMING_FIELD(dphy_timing->lpx, period, 1);
543 writel(value, &ptiming->dsi_phy_timing_1);
544
545 value = DSI_TIMING_FIELD(dphy_timing->clkprepare, period, 1) << 16 |
546 DSI_TIMING_FIELD(dphy_timing->clkpre, period, 1) << 8 |
547 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
548 writel(value, &ptiming->dsi_phy_timing_2);
549
550 value = DSI_TIMING_FIELD(dphy_timing->taget, period, 1) << 16 |
551 DSI_TIMING_FIELD(dphy_timing->tasure, period, 1) << 8 |
552 DSI_TIMING_FIELD(dphy_timing->tago, period, 1);
553 writel(value, &ptiming->dsi_bta_timing);
554 }
555
tegra_dsi_configure(struct udevice * dev,unsigned long mode_flags)556 static void tegra_dsi_configure(struct udevice *dev,
557 unsigned long mode_flags)
558 {
559 struct tegra_dsi_priv *priv = dev_get_priv(dev);
560 struct mipi_dsi_device *device = &priv->device;
561 struct display_timing *timing = &priv->timing;
562
563 struct dsi_misc_reg *misc = &priv->dsi->misc;
564 struct dsi_pkt_seq_reg *pkt = &priv->dsi->pkt;
565 struct dsi_pkt_len_reg *len = &priv->dsi->len;
566
567 unsigned int hact, hsw, hbp, hfp, i, mul, div;
568 const u32 *pkt_seq;
569 u32 value;
570
571 tegra_dsi_get_muldiv(device->format, &mul, &div);
572
573 if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
574 printf("[DSI] Non-burst video mode with sync pulses\n");
575 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
576 } else if (mode_flags & MIPI_DSI_MODE_VIDEO) {
577 printf("[DSI] Non-burst video mode with sync events\n");
578 pkt_seq = pkt_seq_video_non_burst_sync_events;
579 } else {
580 printf("[DSI] Command mode\n");
581 pkt_seq = pkt_seq_command_mode;
582 }
583
584 value = DSI_CONTROL_CHANNEL(0) |
585 DSI_CONTROL_FORMAT(priv->format) |
586 DSI_CONTROL_LANES(device->lanes - 1) |
587 DSI_CONTROL_SOURCE(0);
588 writel(value, &misc->dsi_ctrl);
589
590 writel(priv->video_fifo_depth, &misc->dsi_max_threshold);
591
592 value = DSI_HOST_CONTROL_HS;
593 writel(value, &misc->host_dsi_ctrl);
594
595 value = readl(&misc->dsi_ctrl);
596
597 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
598 value |= DSI_CONTROL_HS_CLK_CTRL;
599
600 value &= ~DSI_CONTROL_TX_TRIG(3);
601
602 /* enable DCS commands for command mode */
603 if (mode_flags & MIPI_DSI_MODE_VIDEO)
604 value &= ~DSI_CONTROL_DCS_ENABLE;
605 else
606 value |= DSI_CONTROL_DCS_ENABLE;
607
608 value |= DSI_CONTROL_VIDEO_ENABLE;
609 value &= ~DSI_CONTROL_HOST_ENABLE;
610 writel(value, &misc->dsi_ctrl);
611
612 for (i = 0; i < NUM_PKT_SEQ; i++)
613 writel(pkt_seq[i], &pkt->dsi_pkt_seq_0_lo + i);
614
615 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
616 /* horizontal active pixels */
617 hact = timing->hactive.typ * mul / div;
618
619 /* horizontal sync width */
620 hsw = timing->hsync_len.typ * mul / div;
621
622 /* horizontal back porch */
623 hbp = timing->hback_porch.typ * mul / div;
624
625 if ((mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
626 hbp += hsw;
627
628 /* horizontal front porch */
629 hfp = timing->hfront_porch.typ * mul / div;
630
631 /* subtract packet overhead */
632 hsw -= 10;
633 hbp -= 14;
634 hfp -= 8;
635
636 writel(hsw << 16 | 0, &len->dsi_pkt_len_0_1);
637 writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3);
638 writel(hfp, &len->dsi_pkt_len_4_5);
639 writel(0x0f0f << 16, &len->dsi_pkt_len_6_7);
640 } else {
641 /* 1 byte (DCS command) + pixel data */
642 value = 1 + timing->hactive.typ * mul / div;
643
644 writel(0, &len->dsi_pkt_len_0_1);
645 writel(value << 16, &len->dsi_pkt_len_2_3);
646 writel(value << 16, &len->dsi_pkt_len_4_5);
647 writel(0, &len->dsi_pkt_len_6_7);
648
649 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
650 MIPI_DCS_WRITE_MEMORY_CONTINUE;
651 writel(value, &len->dsi_dcs_cmds);
652 }
653
654 /* set SOL delay (for non-burst mode only) */
655 writel(8 * mul / div, &misc->dsi_sol_delay);
656 }
657
tegra_dsi_encoder_enable(struct udevice * dev)658 static int tegra_dsi_encoder_enable(struct udevice *dev)
659 {
660 struct tegra_dsi_priv *priv = dev_get_priv(dev);
661 struct mipi_dsi_device *device = &priv->device;
662 struct display_timing *timing = &priv->timing;
663 struct dsi_misc_reg *misc = &priv->dsi->misc;
664 unsigned int mul, div;
665 unsigned long bclk, plld, period;
666 u32 value;
667 int ret;
668
669 /* Disable interrupt */
670 writel(0, &misc->int_enable);
671
672 tegra_dsi_pad_calibrate(&priv->dsi->pad);
673
674 tegra_dsi_get_muldiv(device->format, &mul, &div);
675
676 /* compute byte clock */
677 bclk = (timing->pixelclock.typ * mul) / (div * device->lanes);
678
679 tegra_dsi_set_timeout(&priv->dsi->timeout, bclk, 60);
680
681 /*
682 * Compute bit clock and round up to the next MHz.
683 */
684 plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
685 period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
686
687 ret = mipi_dphy_timing_get_default(&priv->dphy_timing, period);
688 if (ret < 0) {
689 printf("%s: failed to get D-PHY timing: %d\n", __func__, ret);
690 return ret;
691 }
692
693 ret = mipi_dphy_timing_validate(&priv->dphy_timing, period);
694 if (ret < 0) {
695 printf("%s: failed to validate D-PHY timing: %d\n", __func__, ret);
696 return ret;
697 }
698
699 /*
700 * The D-PHY timing fields are expressed in byte-clock cycles, so
701 * multiply the period by 8.
702 */
703 tegra_dsi_set_phy_timing(&priv->dsi->ptiming,
704 period * 8, &priv->dphy_timing);
705
706 /* Perform panel HW setup */
707 ret = panel_enable_backlight(priv->panel);
708 if (ret)
709 return ret;
710
711 tegra_dsi_configure(dev, 0);
712
713 ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
714 if (ret)
715 return ret;
716
717 tegra_dsi_configure(dev, device->mode_flags);
718
719 tegra_dc_enable_controller(dev);
720
721 /* enable DSI controller */
722 value = readl(&misc->dsi_pwr_ctrl);
723 value |= DSI_POWER_CONTROL_ENABLE;
724 writel(value, &misc->dsi_pwr_ctrl);
725
726 return 0;
727 }
728
tegra_dsi_bridge_set_panel(struct udevice * dev,int percent)729 static int tegra_dsi_bridge_set_panel(struct udevice *dev, int percent)
730 {
731 /* Is not used in tegra dc */
732 return 0;
733 }
734
tegra_dsi_panel_timings(struct udevice * dev,struct display_timing * timing)735 static int tegra_dsi_panel_timings(struct udevice *dev,
736 struct display_timing *timing)
737 {
738 struct tegra_dsi_priv *priv = dev_get_priv(dev);
739
740 memcpy(timing, &priv->timing, sizeof(*timing));
741
742 return 0;
743 }
744
tegra_dsi_init_clocks(struct udevice * dev)745 static void tegra_dsi_init_clocks(struct udevice *dev)
746 {
747 struct tegra_dsi_priv *priv = dev_get_priv(dev);
748 struct mipi_dsi_device *device = &priv->device;
749 unsigned int mul, div;
750 unsigned long bclk, plld;
751
752 tegra_dsi_get_muldiv(device->format, &mul, &div);
753
754 bclk = (priv->timing.pixelclock.typ * mul) /
755 (div * device->lanes);
756
757 plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC);
758
759 switch (clock_get_osc_freq()) {
760 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
761 case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
762 clock_set_rate(CLOCK_ID_DISPLAY, plld, 12, 0, 8);
763 break;
764
765 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
766 clock_set_rate(CLOCK_ID_DISPLAY, plld, 26, 0, 8);
767 break;
768
769 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
770 case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
771 clock_set_rate(CLOCK_ID_DISPLAY, plld, 13, 0, 8);
772 break;
773
774 case CLOCK_OSC_FREQ_19_2:
775 case CLOCK_OSC_FREQ_38_4:
776 default:
777 /*
778 * These are not supported.
779 */
780 break;
781 }
782
783 priv->dsi_clk = clock_decode_periph_id(dev);
784
785 clock_enable(priv->dsi_clk);
786 udelay(2);
787 reset_set_enable(priv->dsi_clk, 0);
788 }
789
tegra_dsi_bridge_probe(struct udevice * dev)790 static int tegra_dsi_bridge_probe(struct udevice *dev)
791 {
792 struct tegra_dsi_priv *priv = dev_get_priv(dev);
793 struct mipi_dsi_device *device = &priv->device;
794 struct mipi_dsi_panel_plat *mipi_plat;
795 int ret;
796
797 priv->dsi = (struct dsi_ctlr *)dev_read_addr_ptr(dev);
798 if (!priv->dsi) {
799 printf("%s: No display controller address\n", __func__);
800 return -EINVAL;
801 }
802
803 priv->video_fifo_depth = 480;
804 priv->host_fifo_depth = 64;
805
806 ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
807 "avdd-dsi-csi-supply", &priv->avdd);
808 if (ret)
809 debug("%s: Cannot get avdd-dsi-csi-supply: error %d\n",
810 __func__, ret);
811
812 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
813 "panel", &priv->panel);
814 if (ret) {
815 printf("%s: Cannot get panel: error %d\n", __func__, ret);
816 return log_ret(ret);
817 }
818
819 panel_get_display_timing(priv->panel, &priv->timing);
820
821 mipi_plat = dev_get_plat(priv->panel);
822 mipi_plat->device = device;
823
824 priv->host.dev = (struct device *)dev;
825 priv->host.ops = &tegra_dsi_bridge_host_ops;
826
827 device->host = &priv->host;
828 device->lanes = mipi_plat->lanes;
829 device->format = mipi_plat->format;
830 device->mode_flags = mipi_plat->mode_flags;
831
832 tegra_dsi_get_format(device->format, &priv->format);
833
834 if (priv->avdd) {
835 ret = regulator_set_enable(priv->avdd, true);
836 if (ret)
837 return ret;
838 }
839
840 tegra_dsi_init_clocks(dev);
841
842 return 0;
843 }
844
845 static const struct panel_ops tegra_dsi_bridge_ops = {
846 .enable_backlight = tegra_dsi_encoder_enable,
847 .set_backlight = tegra_dsi_bridge_set_panel,
848 .get_display_timing = tegra_dsi_panel_timings,
849 };
850
851 static const struct udevice_id tegra_dsi_bridge_ids[] = {
852 { .compatible = "nvidia,tegra30-dsi" },
853 { }
854 };
855
856 U_BOOT_DRIVER(tegra_dsi) = {
857 .name = "tegra_dsi",
858 .id = UCLASS_PANEL,
859 .of_match = tegra_dsi_bridge_ids,
860 .ops = &tegra_dsi_bridge_ops,
861 .probe = tegra_dsi_bridge_probe,
862 .plat_auto = sizeof(struct tegra_dc_plat),
863 .priv_auto = sizeof(struct tegra_dsi_priv),
864 };
865