1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell Armada 37xx SoC Watchdog Driver
4 *
5 * Marek Behún <kabel@kernel.org>
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <wdt.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <dm/device_compat.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 struct a37xx_wdt {
20 void __iomem *sel_reg;
21 void __iomem *reg;
22 ulong clk_rate;
23 u64 timeout;
24 };
25
26 /*
27 * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
28 */
29
30 #define CNTR_CTRL(id) ((id) * 0x10)
31 #define CNTR_CTRL_ENABLE 0x0001
32 #define CNTR_CTRL_ACTIVE 0x0002
33 #define CNTR_CTRL_MODE_MASK 0x000c
34 #define CNTR_CTRL_MODE_ONESHOT 0x0000
35 #define CNTR_CTRL_MODE_HWSIG 0x000c
36 #define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
37 #define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
38 #define CNTR_CTRL_PRESCALE_MASK 0xff00
39 #define CNTR_CTRL_PRESCALE_MIN 2
40 #define CNTR_CTRL_PRESCALE_SHIFT 8
41
42 #define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
43 #define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
44
set_counter_value(struct a37xx_wdt * priv,int id,u64 val)45 static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val)
46 {
47 writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id));
48 writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id));
49 }
50
counter_enable(struct a37xx_wdt * priv,int id)51 static void counter_enable(struct a37xx_wdt *priv, int id)
52 {
53 setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
54 }
55
counter_disable(struct a37xx_wdt * priv,int id)56 static void counter_disable(struct a37xx_wdt *priv, int id)
57 {
58 clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
59 }
60
init_counter(struct a37xx_wdt * priv,int id,u32 mode,u32 trig_src)61 static void init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
62 {
63 u32 reg;
64
65 reg = readl(priv->reg + CNTR_CTRL(id));
66
67 reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
68 CNTR_CTRL_TRIG_SRC_MASK);
69
70 /* set mode */
71 reg |= mode;
72
73 /* set prescaler to the min value */
74 reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
75
76 /* set trigger source */
77 reg |= trig_src;
78
79 writel(reg, priv->reg + CNTR_CTRL(id));
80 }
81
a37xx_wdt_reset(struct udevice * dev)82 static int a37xx_wdt_reset(struct udevice *dev)
83 {
84 struct a37xx_wdt *priv = dev_get_priv(dev);
85
86 if (!priv->timeout)
87 return -EINVAL;
88
89 /* counter 1 is retriggered by forcing end count on counter 0 */
90 counter_disable(priv, 0);
91 counter_enable(priv, 0);
92
93 return 0;
94 }
95
a37xx_wdt_expire_now(struct udevice * dev,ulong flags)96 static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)
97 {
98 struct a37xx_wdt *priv = dev_get_priv(dev);
99
100 /* first we set timeout to 0 */
101 counter_disable(priv, 1);
102 set_counter_value(priv, 1, 0);
103 counter_enable(priv, 1);
104
105 /* and then we start counter 1 by forcing end count on counter 0 */
106 counter_disable(priv, 0);
107 counter_enable(priv, 0);
108
109 return 0;
110 }
111
a37xx_wdt_start(struct udevice * dev,u64 ms,ulong flags)112 static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
113 {
114 struct a37xx_wdt *priv = dev_get_priv(dev);
115
116 init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
117 init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG, CNTR_CTRL_TRIG_SRC_PREV_CNTR);
118
119 priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
120
121 set_counter_value(priv, 0, 0);
122 set_counter_value(priv, 1, priv->timeout);
123 counter_enable(priv, 1);
124
125 /* we have to force end count on counter 0 to start counter 1 */
126 counter_enable(priv, 0);
127
128 return 0;
129 }
130
a37xx_wdt_stop(struct udevice * dev)131 static int a37xx_wdt_stop(struct udevice *dev)
132 {
133 struct a37xx_wdt *priv = dev_get_priv(dev);
134
135 counter_disable(priv, 1);
136 counter_disable(priv, 0);
137 writel(0, priv->sel_reg);
138
139 return 0;
140 }
141
a37xx_wdt_probe(struct udevice * dev)142 static int a37xx_wdt_probe(struct udevice *dev)
143 {
144 struct a37xx_wdt *priv = dev_get_priv(dev);
145 fdt_addr_t addr;
146
147 priv->sel_reg = (void __iomem *)MVEBU_REGISTER(0x0d064);
148
149 addr = dev_read_addr(dev);
150 if (addr == FDT_ADDR_T_NONE)
151 goto err;
152 priv->reg = (void __iomem *)addr;
153
154 priv->clk_rate = (ulong)get_ref_clk() * 1000000;
155
156 /*
157 * We use counter 1 as watchdog timer, therefore we only set bit
158 * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on
159 * counter 1.
160 */
161 writel(1 << 1, priv->sel_reg);
162
163 return 0;
164 err:
165 dev_err(dev, "no io address\n");
166 return -ENODEV;
167 }
168
169 static const struct wdt_ops a37xx_wdt_ops = {
170 .start = a37xx_wdt_start,
171 .reset = a37xx_wdt_reset,
172 .stop = a37xx_wdt_stop,
173 .expire_now = a37xx_wdt_expire_now,
174 };
175
176 static const struct udevice_id a37xx_wdt_ids[] = {
177 { .compatible = "marvell,armada-3700-wdt" },
178 {}
179 };
180
181 U_BOOT_DRIVER(a37xx_wdt) = {
182 .name = "armada_37xx_wdt",
183 .id = UCLASS_WDT,
184 .of_match = a37xx_wdt_ids,
185 .probe = a37xx_wdt_probe,
186 .priv_auto = sizeof(struct a37xx_wdt),
187 .ops = &a37xx_wdt_ops,
188 };
189