1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <wdt.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <linux/bitfield.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define CORE0_POKE_OFFSET_MASK 0xfffffULL
19
20 #define WDOG_MODE GENMASK_ULL(1, 0)
21 #define WDOG_LEN GENMASK_ULL(19, 4)
22 #define WDOG_CNT GENMASK_ULL(43, 20)
23
24 struct octeontx_wdt_data {
25 u32 wdog_offset;
26 u32 poke_offset;
27 int timer_shift;
28 bool has_clk;
29 };
30
31 struct octeontx_wdt {
32 void __iomem *reg;
33 const struct octeontx_wdt_data *data;
34 struct clk clk;
35 };
36
octeontx_wdt_start(struct udevice * dev,u64 timeout_ms,ulong flags)37 static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
38 {
39 struct octeontx_wdt *priv = dev_get_priv(dev);
40 u64 clk_rate, val;
41 u64 tout_wdog;
42
43 if (priv->data->has_clk) {
44 clk_rate = clk_get_rate(&priv->clk);
45 if (IS_ERR_VALUE(clk_rate))
46 return -EINVAL;
47 } else {
48 clk_rate = gd->bus_clk;
49 }
50
51 /* Watchdog counts in configured cycle steps */
52 tout_wdog = (clk_rate * timeout_ms / 1000) >> priv->data->timer_shift;
53
54 /*
55 * We can only specify the upper 16 bits of a 24 bit value.
56 * Round up
57 */
58 tout_wdog = (tout_wdog + 0xff) >> 8;
59
60 /* If the timeout overflows the hardware limit, set max */
61 if (tout_wdog >= 0x10000)
62 tout_wdog = 0xffff;
63
64 val = FIELD_PREP(WDOG_MODE, 0x3) |
65 FIELD_PREP(WDOG_LEN, tout_wdog) |
66 FIELD_PREP(WDOG_CNT, tout_wdog << 8);
67 writeq(val, priv->reg + priv->data->wdog_offset);
68
69 return 0;
70 }
71
octeontx_wdt_stop(struct udevice * dev)72 static int octeontx_wdt_stop(struct udevice *dev)
73 {
74 struct octeontx_wdt *priv = dev_get_priv(dev);
75
76 writeq(0, priv->reg + priv->data->wdog_offset);
77
78 return 0;
79 }
80
octeontx_wdt_expire_now(struct udevice * dev,ulong flags)81 static int octeontx_wdt_expire_now(struct udevice *dev, ulong flags)
82 {
83 octeontx_wdt_stop(dev);
84
85 /* Start with 100ms timeout to expire immediately */
86 octeontx_wdt_start(dev, 100, flags);
87
88 return 0;
89 }
90
octeontx_wdt_reset(struct udevice * dev)91 static int octeontx_wdt_reset(struct udevice *dev)
92 {
93 struct octeontx_wdt *priv = dev_get_priv(dev);
94
95 writeq(~0ULL, priv->reg + priv->data->poke_offset);
96
97 return 0;
98 }
99
octeontx_wdt_remove(struct udevice * dev)100 static int octeontx_wdt_remove(struct udevice *dev)
101 {
102 octeontx_wdt_stop(dev);
103
104 return 0;
105 }
106
octeontx_wdt_probe(struct udevice * dev)107 static int octeontx_wdt_probe(struct udevice *dev)
108 {
109 struct octeontx_wdt *priv = dev_get_priv(dev);
110 int ret;
111
112 priv->reg = dev_remap_addr(dev);
113 if (!priv->reg)
114 return -EINVAL;
115
116 priv->data = (void *)dev_get_driver_data(dev);
117 if (!priv->data)
118 return -EINVAL;
119
120 /*
121 * Save base register address in reg masking lower 20 bits
122 * as 0xa0000 appears when extracted from the DT
123 */
124 priv->reg = (void __iomem *)(((u64)priv->reg &
125 ~CORE0_POKE_OFFSET_MASK));
126
127 if (priv->data->has_clk) {
128 ret = clk_get_by_index(dev, 0, &priv->clk);
129 if (ret < 0)
130 return ret;
131
132 ret = clk_enable(&priv->clk);
133 if (ret)
134 return ret;
135 }
136
137 return 0;
138 }
139
140 static const struct wdt_ops octeontx_wdt_ops = {
141 .reset = octeontx_wdt_reset,
142 .start = octeontx_wdt_start,
143 .stop = octeontx_wdt_stop,
144 .expire_now = octeontx_wdt_expire_now,
145 };
146
147 static const struct octeontx_wdt_data octeontx_data = {
148 .wdog_offset = 0x40000,
149 .poke_offset = 0x50000,
150 .timer_shift = 10,
151 .has_clk = true,
152 };
153
154 static const struct octeontx_wdt_data octeon_data = {
155 .wdog_offset = 0x20000,
156 .poke_offset = 0x30000,
157 .timer_shift = 10,
158 .has_clk = false,
159 };
160
161 static const struct udevice_id octeontx_wdt_ids[] = {
162 { .compatible = "arm,sbsa-gwdt", .data = (ulong)&octeontx_data },
163 { .compatible = "cavium,octeon-7890-ciu3", .data = (ulong)&octeon_data },
164 {}
165 };
166
167 U_BOOT_DRIVER(wdt_octeontx) = {
168 .name = "wdt_octeontx",
169 .id = UCLASS_WDT,
170 .of_match = octeontx_wdt_ids,
171 .ops = &octeontx_wdt_ops,
172 .priv_auto = sizeof(struct octeontx_wdt),
173 .probe = octeontx_wdt_probe,
174 .remove = octeontx_wdt_remove,
175 .flags = DM_FLAG_OS_PREPARE,
176 };
177