1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx window watchdog timer driver.
4 *
5 * Author(s): Michal Simek <michal.simek@xilinx.com>
6 * Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
7 *
8 * Copyright (c) 2020, Xilinx Inc.
9 */
10
11 #include <clk.h>
12 #include <common.h>
13 #include <dm.h>
14 #include <regmap.h>
15 #include <wdt.h>
16 #include <linux/compat.h>
17 #include <dm/device_compat.h>
18 #include <linux/io.h>
19
20 /* Refresh Register Masks */
21 #define XWT_WWREF_GWRR_MASK BIT(0) /* Refresh and start new period */
22
23 /* Generic Control/Status Register Masks */
24 #define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */
25
26 /* Register offsets for the WWDT device */
27 #define XWT_WWDT_MWR_OFFSET 0x00
28 #define XWT_WWDT_ESR_OFFSET 0x04
29 #define XWT_WWDT_FCR_OFFSET 0x08
30 #define XWT_WWDT_FWR_OFFSET 0x0c
31 #define XWT_WWDT_SWR_OFFSET 0x10
32 #define XWT_WWDT_CNT_MIN 1
33 #define XWT_WWDT_CNT_MAX 0xffffffff
34
35 /* Master Write Control Register Masks */
36 #define XWT_WWDT_MWR_MASK BIT(0)
37
38 /* Enable and Status Register Masks */
39 #define XWT_WWDT_ESR_WINT_MASK BIT(16)
40 #define XWT_WWDT_ESR_WSW_MASK BIT(8)
41 #define XWT_WWDT_ESR_WEN_MASK BIT(0)
42
43 struct xlnx_wwdt_priv {
44 bool enable_once;
45 struct regmap *regs;
46 struct clk clk;
47 };
48
49 struct xlnx_wwdt_plat {
50 bool enable_once;
51 };
52
xlnx_wwdt_reset(struct udevice * dev)53 static int xlnx_wwdt_reset(struct udevice *dev)
54 {
55 u32 esr;
56 struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
57
58 regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
59 regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
60 esr |= XWT_WWDT_ESR_WINT_MASK;
61 esr &= ~XWT_WWDT_ESR_WSW_MASK;
62 regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
63 regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
64 esr |= XWT_WWDT_ESR_WSW_MASK;
65 regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
66
67 return 0;
68 }
69
xlnx_wwdt_stop(struct udevice * dev)70 static int xlnx_wwdt_stop(struct udevice *dev)
71 {
72 struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
73
74 if (wdt->enable_once) {
75 dev_warn(dev, "Can't stop Xilinx watchdog.\n");
76 return -EBUSY;
77 }
78
79 /* Disable the window watchdog timer */
80 regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
81 regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
82
83 clk_disable(&wdt->clk);
84
85 dev_dbg(dev, "Watchdog disabled!\n");
86
87 return 0;
88 }
89
xlnx_wwdt_start(struct udevice * dev,u64 timeout_ms,ulong flags)90 static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
91 {
92 int ret;
93 u32 esr;
94 u64 count, timeout;
95 unsigned long clock_f;
96 struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
97
98 clock_f = clk_get_rate(&wdt->clk);
99 if (IS_ERR_VALUE(clock_f)) {
100 dev_err(dev, "failed to get rate\n");
101 return clock_f;
102 }
103
104 dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
105
106 /* Convert timeout from msec to sec */
107 timeout = timeout_ms / 1000;
108
109 /* Calculate timeout count */
110 count = timeout * clock_f;
111
112 /* Count should be at least 1 */
113 if (count < XWT_WWDT_CNT_MIN) {
114 debug("%s: watchdog won't fire with 0 ticks\n", __func__);
115 count = XWT_WWDT_CNT_MIN;
116 }
117
118 /* Limit the count to maximum possible value */
119 if (count > XWT_WWDT_CNT_MAX) {
120 debug("%s: maximum watchdog timeout exceeded\n", __func__);
121 count = XWT_WWDT_CNT_MAX;
122 }
123
124 ret = clk_enable(&wdt->clk);
125 if (ret) {
126 dev_err(dev, "failed to enable clock\n");
127 return ret;
128 }
129
130 /* Disable the window watchdog timer */
131 regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
132 regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
133
134 /* Set first window and second window registers with timeout */
135 regmap_write(wdt->regs, XWT_WWDT_FWR_OFFSET, 0); /* No pre-timeout */
136 regmap_write(wdt->regs, XWT_WWDT_SWR_OFFSET, (u32)count);
137 regmap_write(wdt->regs, XWT_WWDT_FCR_OFFSET, 0);
138
139 /* Enable the window watchdog timer */
140 regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
141 esr |= XWT_WWDT_ESR_WEN_MASK;
142 regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
143
144 return 0;
145 }
146
xlnx_wwdt_expire_now(struct udevice * dev,ulong flags)147 static int xlnx_wwdt_expire_now(struct udevice *dev, ulong flags)
148 {
149 return xlnx_wwdt_start(dev, XWT_WWDT_CNT_MIN, flags);
150 }
151
xlnx_wwdt_probe(struct udevice * dev)152 static int xlnx_wwdt_probe(struct udevice *dev)
153 {
154 int ret;
155 struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
156 struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
157
158 dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev_seq(dev));
159
160 ret = regmap_init_mem(dev_ofnode(dev), &wdt->regs);
161 if (ret) {
162 dev_dbg(dev, "failed to get regbase of wwdt\n");
163 return ret;
164 }
165
166 wdt->enable_once = plat->enable_once;
167
168 ret = clk_get_by_index(dev, 0, &wdt->clk);
169 if (ret < 0)
170 dev_err(dev, "failed to get clock\n");
171
172 return ret;
173 }
174
xlnx_wwdt_of_to_plat(struct udevice * dev)175 static int xlnx_wwdt_of_to_plat(struct udevice *dev)
176 {
177 struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
178
179 plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
180 0);
181 dev_dbg(dev, "wdt-enable-once %d\n", plat->enable_once);
182
183 return 0;
184 }
185
186 static const struct wdt_ops xlnx_wwdt_ops = {
187 .start = xlnx_wwdt_start,
188 .reset = xlnx_wwdt_reset,
189 .stop = xlnx_wwdt_stop,
190 .expire_now = xlnx_wwdt_expire_now,
191 };
192
193 static const struct udevice_id xlnx_wwdt_ids[] = {
194 { .compatible = "xlnx,versal-wwdt-1.0", },
195 {},
196 };
197
198 U_BOOT_DRIVER(xlnx_wwdt) = {
199 .name = "xlnx_wwdt",
200 .id = UCLASS_WDT,
201 .of_match = xlnx_wwdt_ids,
202 .probe = xlnx_wwdt_probe,
203 .priv_auto = sizeof(struct xlnx_wwdt_priv),
204 .plat_auto = sizeof(struct xlnx_wwdt_plat),
205 .of_to_plat = xlnx_wwdt_of_to_plat,
206 .ops = &xlnx_wwdt_ops,
207 };
208