1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * Configuation settings for the AT91SAM9263EK board. 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 #include <asm/hardware.h> 20 21 /* ARM asynchronous clock */ 22 #define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 23 #define CFG_SYS_AT91_SLOW_CLOCK 32768 24 25 /* SDRAM */ 26 #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 27 #define CFG_SYS_SDRAM_SIZE 0x04000000 28 29 #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) 30 #define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 31 32 /* NOR flash, if populated */ 33 #ifdef CONFIG_SYS_USE_NORFLASH 34 #define PHYS_FLASH_1 0x10000000 35 #define CFG_SYS_FLASH_BASE PHYS_FLASH_1 36 37 /* Address and size of Primary Environment Sector */ 38 39 #define CFG_EXTRA_ENV_SETTINGS \ 40 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 41 "update=" \ 42 "protect off ${monitor_base} +${filesize};" \ 43 "erase ${monitor_base} +${filesize};" \ 44 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 45 "protect on ${monitor_base} +${filesize}\0" 46 47 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 48 #define MASTER_PLL_MUL 171 49 #define MASTER_PLL_DIV 14 50 #define MASTER_PLL_OUT 3 51 52 /* clocks */ 53 #define CFG_SYS_MOR_VAL \ 54 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 55 #define CFG_SYS_PLLAR_VAL \ 56 (AT91_PMC_PLLAR_29 | \ 57 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 58 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 59 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 60 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 61 62 /* PCK/2 = MCK Master Clock from PLLA */ 63 #define CFG_SYS_MCKR1_VAL \ 64 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 65 AT91_PMC_MCKR_MDIV_2) 66 67 /* PCK/2 = MCK Master Clock from PLLA */ 68 #define CFG_SYS_MCKR2_VAL \ 69 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 70 AT91_PMC_MCKR_MDIV_2) 71 72 /* define PDC[31:16] as DATA[31:16] */ 73 #define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 74 /* no pull-up for D[31:16] */ 75 #define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 76 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 77 #define CFG_SYS_MATRIX_EBICSA_VAL \ 78 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 79 AT91_MATRIX_CSA_EBI_CS1A) 80 81 /* SDRAM */ 82 /* SDRAMC_MR Mode register */ 83 #define CFG_SYS_SDRC_MR_VAL1 0 84 /* SDRAMC_TR - Refresh Timer register */ 85 #define CFG_SYS_SDRC_TR_VAL1 0x13C 86 /* SDRAMC_CR - Configuration register*/ 87 #define CFG_SYS_SDRC_CR_VAL \ 88 (AT91_SDRAMC_NC_9 | \ 89 AT91_SDRAMC_NR_13 | \ 90 AT91_SDRAMC_NB_4 | \ 91 AT91_SDRAMC_CAS_3 | \ 92 AT91_SDRAMC_DBW_32 | \ 93 (1 << 8) | /* Write Recovery Delay */ \ 94 (7 << 12) | /* Row Cycle Delay */ \ 95 (2 << 16) | /* Row Precharge Delay */ \ 96 (2 << 20) | /* Row to Column Delay */ \ 97 (5 << 24) | /* Active to Precharge Delay */ \ 98 (1 << 28)) /* Exit Self Refresh to Active Delay */ 99 100 /* Memory Device Register -> SDRAM */ 101 #define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 102 #define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 103 #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 104 #define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 105 #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 106 #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 107 #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 108 #define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 109 #define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 110 #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 111 #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 112 #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 113 #define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 114 #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 115 #define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 116 #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 117 #define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 118 #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 119 120 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 121 #define CFG_SYS_SMC0_SETUP0_VAL \ 122 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 123 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 124 #define CFG_SYS_SMC0_PULSE0_VAL \ 125 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 126 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 127 #define CFG_SYS_SMC0_CYCLE0_VAL \ 128 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 129 #define CFG_SYS_SMC0_MODE0_VAL \ 130 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 131 AT91_SMC_MODE_DBW_16 | \ 132 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 133 134 /* user reset enable */ 135 #define CFG_SYS_RSTC_RMR_VAL \ 136 (AT91_RSTC_KEY | \ 137 AT91_RSTC_MR_URSTEN | \ 138 AT91_RSTC_MR_ERSTL(15)) 139 140 /* Disable Watchdog */ 141 #define CFG_SYS_WDTC_WDMR_VAL \ 142 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 143 AT91_WDT_MR_WDV(0xfff) | \ 144 AT91_WDT_MR_WDDIS | \ 145 AT91_WDT_MR_WDD(0xfff)) 146 147 #endif 148 #include <linux/stringify.h> 149 #endif 150 151 /* NAND flash */ 152 #ifdef CONFIG_CMD_NAND 153 #define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 154 /* our ALE is AD21 */ 155 #define CFG_SYS_NAND_MASK_ALE (1 << 21) 156 /* our CLE is AD22 */ 157 #define CFG_SYS_NAND_MASK_CLE (1 << 22) 158 #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 159 #define CFG_SYS_NAND_READY_PIN AT91_PIN_PA22 160 #endif 161 162 /* USB */ 163 #define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 164 165 #endif 166