1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  * Copyright 2019 NXP
5  */
6 
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9 
10 #define CFG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
11 #define CFG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
12 
13 /*
14  * DDR: 800 MHz ( 1600 MT/s data rate )
15  */
16 
17 #define DDR_SDRAM_CFG			0x470c0008
18 #define DDR_CS0_BNDS			0x008000bf
19 #define DDR_CS0_CONFIG			0x80014302
20 #define DDR_TIMING_CFG_0		0x50550004
21 #define DDR_TIMING_CFG_1		0xbcb38c56
22 #define DDR_TIMING_CFG_2		0x0040d120
23 #define DDR_TIMING_CFG_3		0x010e1000
24 #define DDR_TIMING_CFG_4		0x00000001
25 #define DDR_TIMING_CFG_5		0x03401400
26 #define DDR_SDRAM_CFG_2			0x00401010
27 #define DDR_SDRAM_MODE			0x00061c60
28 #define DDR_SDRAM_MODE_2		0x00180000
29 #define DDR_SDRAM_INTERVAL		0x18600618
30 #define DDR_DDR_WRLVL_CNTL		0x8655f605
31 #define DDR_DDR_WRLVL_CNTL_2	0x05060607
32 #define DDR_DDR_WRLVL_CNTL_3	0x05050505
33 #define DDR_DDR_CDR1			0x80040000
34 #define DDR_DDR_CDR2			0x00000001
35 #define DDR_SDRAM_CLK_CNTL		0x02000000
36 #define DDR_DDR_ZQ_CNTL			0x89080600
37 #define DDR_CS0_CONFIG_2		0
38 #define DDR_SDRAM_CFG_MEM_EN	0x80000000
39 #define SDRAM_CFG2_D_INIT		0x00000010
40 #define DDR_CDR2_VREF_TRAIN_EN	0x00000080
41 #define SDRAM_CFG2_FRC_SR		0x80000000
42 #define SDRAM_CFG_BI			0x00000001
43 
44 #define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
45 #define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
46 
47 /*
48  * Serial Port
49  */
50 #define CFG_SYS_NS16550_CLK		get_serial_clock()
51 
52 /*
53  * I2C
54  */
55 
56 /*
57  * MMC
58  */
59 
60 /* SATA */
61 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
62 #define PCI_DEVICE_ID_FREESCALE_AHCI	0x0440
63 #endif
64 #define CFG_SCSI_DEV_LIST		{PCI_VENDOR_ID_FREESCALE, \
65 	PCI_DEVICE_ID_FREESCALE_AHCI}
66 
67 /* SPI */
68 
69 #define FSL_PCIE_COMPAT		"fsl,ls1021a-pcie"
70 
71 #define CFG_SMP_PEN_ADDR		0x01ee0200
72 
73 #define HWCONFIG_BUFFER_SIZE		256
74 
75 #define CFG_EXTRA_ENV_SETTINGS	\
76 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
77 "initrd_high=0xffffffff\0"
78 
79 /*
80  * Miscellaneous configurable options
81  */
82 #define CFG_SYS_BOOTMAPSZ		(256 << 20)
83 
84 #include <asm/fsl_secure_boot.h>
85 
86 #endif
87