1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright (C) 2014 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #include <asm/arch/stream_id_lsch3.h> 11 #include <asm/arch/config.h> 12 13 /* Link Definitions */ 14 15 /* We need architecture specific misc initializations */ 16 17 /* Link Definitions */ 18 19 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL 20 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 21 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 22 #define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 23 24 /* 25 * SMP Definitinos 26 */ 27 #define CPU_RELEASE_ADDR secondary_boot_addr 28 29 /* 30 * This is not an accurate number. It is used in start.S. The frequency 31 * will be udpated later when get_bus_freq(0) is available. 32 */ 33 34 /* GPIO */ 35 36 /* I2C */ 37 38 /* Serial Port */ 39 #define CFG_SYS_NS16550_CLK (get_serial_clock()) 40 41 /* 42 * During booting, IFC is mapped at the region of 0x30000000. 43 * But this region is limited to 256MB. To accommodate NOR, promjet 44 * and FPGA. This region is divided as below: 45 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 46 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 47 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 48 * 49 * To accommodate bigger NOR flash and other devices, we will map IFC 50 * chip selects to as below: 51 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 52 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 53 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 54 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 55 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 56 * 57 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 58 * CFG_SYS_FLASH_BASE has the final address (core view) 59 * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 60 * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 61 * CONFIG_TEXT_BASE is linked to 0x30000000 for booting 62 */ 63 64 #define CFG_SYS_FLASH_BASE 0x580000000ULL 65 #define CFG_SYS_FLASH_BASE_PHYS 0x80000000 66 #define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 67 68 #define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 69 #define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 70 71 #ifndef __ASSEMBLY__ 72 unsigned long long get_qixis_addr(void); 73 #endif 74 #define QIXIS_BASE get_qixis_addr() 75 #define QIXIS_BASE_PHYS 0x20000000 76 #define QIXIS_BASE_PHYS_EARLY 0xC000000 77 #define QIXIS_STAT_PRES1 0xb 78 #define QIXIS_SDID_MASK 0x07 79 #define QIXIS_ESDHC_NO_ADAPTER 0x7 80 81 #define CFG_SYS_NAND_BASE 0x530000000ULL 82 #define CFG_SYS_NAND_BASE_PHYS 0x30000000 83 84 /* MC firmware */ 85 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 86 #define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 87 #define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 88 #define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 89 #define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 90 /* For LS2085A */ 91 #define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 92 #define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 93 94 /* 95 * Carve out a DDR region which will not be used by u-boot/Linux 96 * 97 * It will be used by MC and Debug Server. The MC region must be 98 * 512MB aligned, so the min size to hide is 512MB. 99 */ 100 #ifdef CONFIG_FSL_MC_ENET 101 #define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) 102 #endif 103 104 /* Miscellaneous configurable options */ 105 106 /* Physical Memory Map */ 107 /* fixme: these need to be checked against the board */ 108 109 #define HWCONFIG_BUFFER_SIZE 128 110 111 /* Initial environment variables */ 112 #define CFG_EXTRA_ENV_SETTINGS \ 113 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 114 "loadaddr=0x80100000\0" \ 115 "kernel_addr=0x100000\0" \ 116 "ramdisk_addr=0x800000\0" \ 117 "ramdisk_size=0x2000000\0" \ 118 "fdt_high=0xa0000000\0" \ 119 "initrd_high=0xffffffffffffffff\0" \ 120 "kernel_start=0x581000000\0" \ 121 "kernel_load=0xa0000000\0" \ 122 "kernel_size=0x2800000\0" \ 123 "console=ttyAMA0,38400n8\0" \ 124 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 125 " 0x580e00000 \0" 126 127 #ifdef CONFIG_NAND_BOOT 128 #define CFG_SYS_NAND_U_BOOT_DST 0x80400000 129 #define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST 130 #endif 131 132 #include <asm/arch/soc.h> 133 134 #endif /* __LS2_COMMON_H */ 135