1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018-2021 NXP 4 */ 5 6 #ifndef __LX2_COMMON_H 7 #define __LX2_COMMON_H 8 9 #include <asm/arch/stream_id_lsch3.h> 10 #include <asm/arch/config.h> 11 #include <asm/arch/soc.h> 12 13 #define CFG_SYS_FLASH_BASE 0x20000000 14 15 /* DDR */ 16 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL 17 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 18 #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL 19 #define CFG_SYS_SDRAM_SIZE 0x200000000UL 20 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 21 #define SPD_EEPROM_ADDRESS1 0x51 22 #define SPD_EEPROM_ADDRESS2 0x52 23 #define SPD_EEPROM_ADDRESS3 0x53 24 #define SPD_EEPROM_ADDRESS4 0x54 25 #define SPD_EEPROM_ADDRESS5 0x55 26 #define SPD_EEPROM_ADDRESS6 0x56 27 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 28 29 /* Miscellaneous configurable options */ 30 31 /* SMP Definitinos */ 32 #define CPU_RELEASE_ADDR secondary_boot_addr 33 34 /* Generic Timer Definitions */ 35 /* 36 * This is not an accurate number. It is used in start.S. The frequency 37 * will be udpated later when get_bus_freq(0) is available. 38 */ 39 40 41 /* Serial Port */ 42 #define CFG_PL011_CLOCK (get_bus_freq(0) / 4) 43 #define CFG_SYS_SERIAL0 0x21c0000 44 #define CFG_SYS_SERIAL1 0x21d0000 45 #define CFG_SYS_SERIAL2 0x21e0000 46 #define CFG_SYS_SERIAL3 0x21f0000 47 /*below might needs to be removed*/ 48 #define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ 49 (void *)CFG_SYS_SERIAL1, \ 50 (void *)CFG_SYS_SERIAL2, \ 51 (void *)CFG_SYS_SERIAL3 } 52 53 /* MC firmware */ 54 #define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 55 #define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 56 #define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 57 #define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 58 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 59 60 /* 61 * Carve out a DDR region which will not be used by u-boot/Linux 62 * 63 * It will be used by MC and Debug Server. The MC region must be 64 * 512MB aligned, so the min size to hide is 512MB. 65 */ 66 #ifdef CONFIG_FSL_MC_ENET 67 #define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) 68 #endif 69 70 /* I2C bus multiplexer */ 71 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 72 #define I2C_MUX_CH_DEFAULT 0x8 73 74 /* RTC */ 75 #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 76 77 /* Qixis */ 78 #define CFG_SYS_I2C_FPGA_ADDR 0x66 79 80 /* USB */ 81 82 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) 83 84 #define HWCONFIG_BUFFER_SIZE 128 85 86 /* Initial environment variables */ 87 #define XSPI_MC_INIT_CMD \ 88 "sf probe 0:0 && " \ 89 "sf read 0x80640000 0x640000 0x80000 && " \ 90 "sf read $fdt_addr_r 0xf00000 0x100000 && " \ 91 "env exists secureboot && " \ 92 "esbc_validate 0x80640000 && " \ 93 "esbc_validate 0x80680000; " \ 94 "sf read 0x80a00000 0xa00000 0x300000 && " \ 95 "sf read 0x80e00000 0xe00000 0x100000; " \ 96 "fsl_mc start mc 0x80a00000 0x80e00000\0" 97 98 #define SD_MC_INIT_CMD \ 99 "mmc read 0x80a00000 0x5000 0x1200;" \ 100 "mmc read 0x80e00000 0x7000 0x800;" \ 101 "mmc read $fdt_addr_r 0x7800 0x800;" \ 102 "env exists secureboot && " \ 103 "mmc read 0x80640000 0x3200 0x20 && " \ 104 "mmc read 0x80680000 0x3400 0x20 && " \ 105 "esbc_validate 0x80640000 && " \ 106 "esbc_validate 0x80680000 ;" \ 107 "fsl_mc start mc 0x80a00000 0x80e00000\0" 108 109 #define SD2_MC_INIT_CMD \ 110 "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \ 111 "mmc read 0x80e00000 0x7000 0x800;" \ 112 "mmc read $fdt_addr_r 0x7800 0x800;" \ 113 "env exists secureboot && " \ 114 "mmc read 0x80640000 0x3200 0x20 && " \ 115 "mmc read 0x80680000 0x3400 0x20 && " \ 116 "esbc_validate 0x80640000 && " \ 117 "esbc_validate 0x80680000 ;" \ 118 "fsl_mc start mc 0x80a00000 0x80e00000\0" 119 120 #define EXTRA_ENV_SETTINGS \ 121 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 122 "ramdisk_addr=0x800000\0" \ 123 "ramdisk_size=0x2000000\0" \ 124 "fdt_high=0xa0000000\0" \ 125 "initrd_high=0xffffffffffffffff\0" \ 126 "kernel_start=0x1000000\0" \ 127 "kernelheader_start=0x600000\0" \ 128 "scriptaddr=0x80000000\0" \ 129 "scripthdraddr=0x80080000\0" \ 130 "fdtheader_addr_r=0x80100000\0" \ 131 "kernelheader_addr_r=0x80200000\0" \ 132 "kernel_addr_r=0x81000000\0" \ 133 "kernelheader_size=0x40000\0" \ 134 "fdt_addr_r=0x90000000\0" \ 135 "load_addr=0xa0000000\0" \ 136 "kernel_size=0x2800000\0" \ 137 "kernel_addr_sd=0x8000\0" \ 138 "kernelhdr_addr_sd=0x3000\0" \ 139 "kernel_size_sd=0x14000\0" \ 140 "kernelhdr_size_sd=0x20\0" \ 141 "console=ttyAMA0,38400n8\0" \ 142 BOOTENV \ 143 "mcmemsize=0x70000000\0" \ 144 XSPI_MC_INIT_CMD \ 145 "scan_dev_for_boot_part=" \ 146 "part list ${devtype} ${devnum} devplist; " \ 147 "env exists devplist || setenv devplist 1; " \ 148 "for distro_bootpart in ${devplist}; do " \ 149 "if fstype ${devtype} " \ 150 "${devnum}:${distro_bootpart} " \ 151 "bootfstype; then " \ 152 "run scan_dev_for_boot; " \ 153 "fi; " \ 154 "done\0" \ 155 "boot_a_script=" \ 156 "load ${devtype} ${devnum}:${distro_bootpart} " \ 157 "${scriptaddr} ${prefix}${script}; " \ 158 "env exists secureboot && load ${devtype} " \ 159 "${devnum}:${distro_bootpart} " \ 160 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 161 "&& esbc_validate ${scripthdraddr};" \ 162 "source ${scriptaddr}\0" 163 164 #define XSPI_NOR_BOOTCOMMAND \ 165 "sf probe 0:0; " \ 166 "sf read 0x806c0000 0x6c0000 0x40000; " \ 167 "env exists mcinitcmd && env exists secureboot" \ 168 " && esbc_validate 0x806c0000; " \ 169 "sf read 0x80d00000 0xd00000 0x100000; " \ 170 "env exists mcinitcmd && " \ 171 "fsl_mc lazyapply dpl 0x80d00000; " \ 172 "run distro_bootcmd;run xspi_bootcmd; " \ 173 "env exists secureboot && esbc_halt;" 174 175 #define SD_BOOTCOMMAND \ 176 "env exists mcinitcmd && mmcinfo; " \ 177 "mmc read 0x80d00000 0x6800 0x800; " \ 178 "env exists mcinitcmd && env exists secureboot " \ 179 " && mmc read 0x806C0000 0x3600 0x20 " \ 180 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ 181 "&& fsl_mc lazyapply dpl 0x80d00000;" \ 182 "run distro_bootcmd;run sd_bootcmd;" \ 183 "env exists secureboot && esbc_halt;" 184 185 #define SD2_BOOTCOMMAND \ 186 "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ 187 "mmc read 0x80d00000 0x6800 0x800; " \ 188 "env exists mcinitcmd && env exists secureboot " \ 189 " && mmc read 0x806C0000 0x3600 0x20 " \ 190 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ 191 "&& fsl_mc lazyapply dpl 0x80d00000;" \ 192 "run distro_bootcmd;run sd2_bootcmd;" \ 193 "env exists secureboot && esbc_halt;" 194 195 #ifdef CONFIG_CMD_USB 196 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) 197 #else 198 #define BOOT_TARGET_DEVICES_USB(func) 199 #endif 200 201 #ifdef CONFIG_MMC 202 #define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance) 203 #else 204 #define BOOT_TARGET_DEVICES_MMC(func) 205 #endif 206 207 #ifdef CONFIG_SCSI 208 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) 209 #else 210 #define BOOT_TARGET_DEVICES_SCSI(func) 211 #endif 212 213 #ifdef CONFIG_CMD_DHCP 214 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 215 #else 216 #define BOOT_TARGET_DEVICES_DHCP(func) 217 #endif 218 219 #define BOOT_TARGET_DEVICES(func) \ 220 BOOT_TARGET_DEVICES_USB(func) \ 221 BOOT_TARGET_DEVICES_MMC(func, 0) \ 222 BOOT_TARGET_DEVICES_MMC(func, 1) \ 223 BOOT_TARGET_DEVICES_SCSI(func) \ 224 BOOT_TARGET_DEVICES_DHCP(func) 225 #include <config_distro_bootcmd.h> 226 227 #endif /* __LX2_COMMON_H */ 228