1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2019-2020
4  * Marvell <www.marvell.com>
5  */
6 
7 #ifndef __OCTEON_COMMON_H__
8 #define __OCTEON_COMMON_H__
9 
10 #if defined(CONFIG_RAM_OCTEON)
11 #define CFG_SYS_INIT_SP_OFFSET	0x20180000
12 #else
13 /* No DDR init -> run in L2 cache with limited resources */
14 #define CFG_SYS_INIT_SP_OFFSET	0x00180000
15 #endif
16 
17 #define CFG_SYS_SDRAM_BASE		0xffffffff80000000
18 
19 #endif /* __OCTEON_COMMON_H__ */
20