1 /* SPDX-License-Identifier:     GPL-2.0+ */
2 /*
3  * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4  */
5 
6 #ifndef __CONFIG_RK3568_COMMON_H
7 #define __CONFIG_RK3568_COMMON_H
8 
9 #define CFG_CPUID_OFFSET	0xa
10 
11 #include "rockchip-common.h"
12 
13 #define CFG_IRAM_BASE		0xfdcc0000
14 
15 #define CFG_SYS_SDRAM_BASE		0
16 #define SDRAM_MAX_SIZE			0xf0000000
17 
18 #define ENV_MEM_LAYOUT_SETTINGS		\
19 	"scriptaddr=0x00c00000\0"	\
20 	"script_offset_f=0xffe000\0"	\
21 	"script_size_f=0x2000\0"	\
22 	"pxefile_addr_r=0x00e00000\0"	\
23 	"fdt_addr_r=0x0a100000\0"	\
24 	"fdtoverlay_addr_r=0x02000000\0"	\
25 	"kernel_addr_r=0x02080000\0"	\
26 	"ramdisk_addr_r=0x0a200000\0"	\
27 	"kernel_comp_addr_r=0x08000000\0"	\
28 	"kernel_comp_size=0x2000000\0"
29 
30 #define CFG_EXTRA_ENV_SETTINGS		\
31 	ENV_MEM_LAYOUT_SETTINGS			\
32 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
33 	"partitions=" PARTS_DEFAULT		\
34 	ROCKCHIP_DEVICE_SETTINGS \
35 	"boot_targets=" BOOT_TARGETS "\0"
36 
37 #endif
38