1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 4 * Copyright (C) 2022 StarFive Technology Co., Ltd. 5 */ 6 7 #ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ 8 #define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ 9 10 /* 11 * mux bits: 12 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | 13 * | din | dout | doen | function | gpio nr | 14 * 15 * dout: output signal 16 * doen: output enable signal 17 * din: optional input signal, 0xff = none 18 * function: 19 * gpio nr: gpio number, 0 - 63 20 */ 21 #define GPIOMUX(n, dout, doen, din) ( \ 22 (((din) & 0xff) << 24) | \ 23 (((dout) & 0xff) << 16) | \ 24 (((doen) & 0x3f) << 10) | \ 25 ((n) & 0x3f)) 26 27 #define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) 28 29 /* sys_iomux pin */ 30 #define PAD_GPIO0 0 31 #define PAD_GPIO1 1 32 #define PAD_GPIO2 2 33 #define PAD_GPIO3 3 34 #define PAD_GPIO4 4 35 #define PAD_GPIO5 5 36 #define PAD_GPIO6 6 37 #define PAD_GPIO7 7 38 #define PAD_GPIO8 8 39 #define PAD_GPIO9 9 40 #define PAD_GPIO10 10 41 #define PAD_GPIO11 11 42 #define PAD_GPIO12 12 43 #define PAD_GPIO13 13 44 #define PAD_GPIO14 14 45 #define PAD_GPIO15 15 46 #define PAD_GPIO16 16 47 #define PAD_GPIO17 17 48 #define PAD_GPIO18 18 49 #define PAD_GPIO19 19 50 #define PAD_GPIO20 20 51 #define PAD_GPIO21 21 52 #define PAD_GPIO22 22 53 #define PAD_GPIO23 23 54 #define PAD_GPIO24 24 55 #define PAD_GPIO25 25 56 #define PAD_GPIO26 26 57 #define PAD_GPIO27 27 58 #define PAD_GPIO28 28 59 #define PAD_GPIO29 29 60 #define PAD_GPIO30 30 61 #define PAD_GPIO31 31 62 #define PAD_GPIO32 32 63 #define PAD_GPIO33 33 64 #define PAD_GPIO34 34 65 #define PAD_GPIO35 35 66 #define PAD_GPIO36 36 67 #define PAD_GPIO37 37 68 #define PAD_GPIO38 38 69 #define PAD_GPIO39 39 70 #define PAD_GPIO40 40 71 #define PAD_GPIO41 41 72 #define PAD_GPIO42 42 73 #define PAD_GPIO43 43 74 #define PAD_GPIO44 44 75 #define PAD_GPIO45 45 76 #define PAD_GPIO46 46 77 #define PAD_GPIO47 47 78 #define PAD_GPIO48 48 79 #define PAD_GPIO49 49 80 #define PAD_GPIO50 50 81 #define PAD_GPIO51 51 82 #define PAD_GPIO52 52 83 #define PAD_GPIO53 53 84 #define PAD_GPIO54 54 85 #define PAD_GPIO55 55 86 #define PAD_GPIO56 56 87 #define PAD_GPIO57 57 88 #define PAD_GPIO58 58 89 #define PAD_GPIO59 59 90 #define PAD_GPIO60 60 91 #define PAD_GPIO61 61 92 #define PAD_GPIO62 62 93 #define PAD_GPIO63 63 94 #define PAD_SD0_CLK 64 95 #define PAD_SD0_CMD 65 96 #define PAD_SD0_DATA0 66 97 #define PAD_SD0_DATA1 67 98 #define PAD_SD0_DATA2 68 99 #define PAD_SD0_DATA3 69 100 #define PAD_SD0_DATA4 70 101 #define PAD_SD0_DATA5 71 102 #define PAD_SD0_DATA6 72 103 #define PAD_SD0_DATA7 73 104 #define PAD_SD0_STRB 74 105 #define PAD_GMAC1_MDC 75 106 #define PAD_GMAC1_MDIO 76 107 #define PAD_GMAC1_RXD0 77 108 #define PAD_GMAC1_RXD1 78 109 #define PAD_GMAC1_RXD2 79 110 #define PAD_GMAC1_RXD3 80 111 #define PAD_GMAC1_RXDV 81 112 #define PAD_GMAC1_RXC 82 113 #define PAD_GMAC1_TXD0 83 114 #define PAD_GMAC1_TXD1 84 115 #define PAD_GMAC1_TXD2 85 116 #define PAD_GMAC1_TXD3 86 117 #define PAD_GMAC1_TXEN 87 118 #define PAD_GMAC1_TXC 88 119 #define PAD_QSPI_SCLK 89 120 #define PAD_QSPI_CS0 90 121 #define PAD_QSPI_DATA0 91 122 #define PAD_QSPI_DATA1 92 123 #define PAD_QSPI_DATA2 93 124 #define PAD_QSPI_DATA3 94 125 126 /* aon_iomux pin */ 127 #define PAD_TESTEN 0 128 #define PAD_RGPIO0 1 129 #define PAD_RGPIO1 2 130 #define PAD_RGPIO2 3 131 #define PAD_RGPIO3 4 132 #define PAD_RSTN 5 133 #define PAD_GMAC0_MDC 6 134 #define PAD_GMAC0_MDIO 7 135 #define PAD_GMAC0_RXD0 8 136 #define PAD_GMAC0_RXD1 9 137 #define PAD_GMAC0_RXD2 10 138 #define PAD_GMAC0_RXD3 11 139 #define PAD_GMAC0_RXDV 12 140 #define PAD_GMAC0_RXC 13 141 #define PAD_GMAC0_TXD0 14 142 #define PAD_GMAC0_TXD1 15 143 #define PAD_GMAC0_TXD2 16 144 #define PAD_GMAC0_TXD3 17 145 #define PAD_GMAC0_TXEN 18 146 #define PAD_GMAC0_TXC 19 147 148 /* sys_iomux dout */ 149 #define GPOUT_LOW 0 150 #define GPOUT_HIGH 1 151 #define GPOUT_SYS_WAVE511_UART_TX 2 152 #define GPOUT_SYS_CAN0_STBY 3 153 #define GPOUT_SYS_CAN0_TST_NEXT_BIT 4 154 #define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5 155 #define GPOUT_SYS_CAN0_TXD 6 156 #define GPOUT_SYS_USB_DRIVE_VBUS 7 157 #define GPOUT_SYS_QSPI_CS1 8 158 #define GPOUT_SYS_SPDIF 9 159 #define GPOUT_SYS_HDMI_CEC_SDA 10 160 #define GPOUT_SYS_HDMI_DDC_SCL 11 161 #define GPOUT_SYS_HDMI_DDC_SDA 12 162 #define GPOUT_SYS_WATCHDOG 13 163 #define GPOUT_SYS_I2C0_CLK 14 164 #define GPOUT_SYS_I2C0_DATA 15 165 #define GPOUT_SYS_SDIO0_BACK_END_POWER 16 166 #define GPOUT_SYS_SDIO0_CARD_POWER_EN 17 167 #define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18 168 #define GPOUT_SYS_SDIO0_RST 19 169 #define GPOUT_SYS_UART0_TX 20 170 #define GPOUT_SYS_HIFI4_JTAG_TDO 21 171 #define GPOUT_SYS_JTAG_TDO 22 172 #define GPOUT_SYS_PDM_MCLK 23 173 #define GPOUT_SYS_PWM_CHANNEL0 24 174 #define GPOUT_SYS_PWM_CHANNEL1 25 175 #define GPOUT_SYS_PWM_CHANNEL2 26 176 #define GPOUT_SYS_PWM_CHANNEL3 27 177 #define GPOUT_SYS_PWMDAC_LEFT 28 178 #define GPOUT_SYS_PWMDAC_RIGHT 29 179 #define GPOUT_SYS_SPI0_CLK 30 180 #define GPOUT_SYS_SPI0_FSS 31 181 #define GPOUT_SYS_SPI0_TXD 32 182 #define GPOUT_SYS_GMAC_PHYCLK 33 183 #define GPOUT_SYS_I2SRX_BCLK 34 184 #define GPOUT_SYS_I2SRX_LRCK 35 185 #define GPOUT_SYS_I2STX0_BCLK 36 186 #define GPOUT_SYS_I2STX0_LRCK 37 187 #define GPOUT_SYS_MCLK 38 188 #define GPOUT_SYS_TDM_CLK 39 189 #define GPOUT_SYS_TDM_SYNC 40 190 #define GPOUT_SYS_TDM_TXD 41 191 #define GPOUT_SYS_TRACE_DATA0 42 192 #define GPOUT_SYS_TRACE_DATA1 43 193 #define GPOUT_SYS_TRACE_DATA2 44 194 #define GPOUT_SYS_TRACE_DATA3 45 195 #define GPOUT_SYS_TRACE_REF 46 196 #define GPOUT_SYS_CAN1_STBY 47 197 #define GPOUT_SYS_CAN1_TST_NEXT_BIT 48 198 #define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49 199 #define GPOUT_SYS_CAN1_TXD 50 200 #define GPOUT_SYS_I2C1_CLK 51 201 #define GPOUT_SYS_I2C1_DATA 52 202 #define GPOUT_SYS_SDIO1_BACK_END_POWER 53 203 #define GPOUT_SYS_SDIO1_CARD_POWER_EN 54 204 #define GPOUT_SYS_SDIO1_CLK 55 205 #define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56 206 #define GPOUT_SYS_SDIO1_CMD 57 207 #define GPOUT_SYS_SDIO1_DATA0 58 208 #define GPOUT_SYS_SDIO1_DATA1 59 209 #define GPOUT_SYS_SDIO1_DATA2 60 210 #define GPOUT_SYS_SDIO1_DATA3 61 211 #define GPOUT_SYS_SDIO1_DATA4 63 212 #define GPOUT_SYS_SDIO1_DATA5 63 213 #define GPOUT_SYS_SDIO1_DATA6 64 214 #define GPOUT_SYS_SDIO1_DATA7 65 215 #define GPOUT_SYS_SDIO1_RST 66 216 #define GPOUT_SYS_UART1_RTS 67 217 #define GPOUT_SYS_UART1_TX 68 218 #define GPOUT_SYS_I2STX1_SDO0 69 219 #define GPOUT_SYS_I2STX1_SDO1 70 220 #define GPOUT_SYS_I2STX1_SDO2 71 221 #define GPOUT_SYS_I2STX1_SDO3 72 222 #define GPOUT_SYS_SPI1_CLK 73 223 #define GPOUT_SYS_SPI1_FSS 74 224 #define GPOUT_SYS_SPI1_TXD 75 225 #define GPOUT_SYS_I2C2_CLK 76 226 #define GPOUT_SYS_I2C2_DATA 77 227 #define GPOUT_SYS_UART2_RTS 78 228 #define GPOUT_SYS_UART2_TX 79 229 #define GPOUT_SYS_SPI2_CLK 80 230 #define GPOUT_SYS_SPI2_FSS 81 231 #define GPOUT_SYS_SPI2_TXD 82 232 #define GPOUT_SYS_I2C3_CLK 83 233 #define GPOUT_SYS_I2C3_DATA 84 234 #define GPOUT_SYS_UART3_TX 85 235 #define GPOUT_SYS_SPI3_CLK 86 236 #define GPOUT_SYS_SPI3_FSS 87 237 #define GPOUT_SYS_SPI3_TXD 88 238 #define GPOUT_SYS_I2C4_CLK 89 239 #define GPOUT_SYS_I2C4_DATA 90 240 #define GPOUT_SYS_UART4_RTS 91 241 #define GPOUT_SYS_UART4_TX 92 242 #define GPOUT_SYS_SPI4_CLK 93 243 #define GPOUT_SYS_SPI4_FSS 94 244 #define GPOUT_SYS_SPI4_TXD 95 245 #define GPOUT_SYS_I2C5_CLK 96 246 #define GPOUT_SYS_I2C5_DATA 97 247 #define GPOUT_SYS_UART5_RTS 98 248 #define GPOUT_SYS_UART5_TX 99 249 #define GPOUT_SYS_SPI5_CLK 100 250 #define GPOUT_SYS_SPI5_FSS 101 251 #define GPOUT_SYS_SPI5_TXD 102 252 #define GPOUT_SYS_I2C6_CLK 103 253 #define GPOUT_SYS_I2C6_DATA 104 254 #define GPOUT_SYS_SPI6_CLK 105 255 #define GPOUT_SYS_SPI6_FSS 106 256 #define GPOUT_SYS_SPI6_TXD 107 257 258 /* aon_iomux dout */ 259 #define GPOUT_AON_CLK_32K_OUT 2 260 #define GPOUT_AON_PTC0_PWM4 3 261 #define GPOUT_AON_PTC0_PWM5 4 262 #define GPOUT_AON_PTC0_PWM6 5 263 #define GPOUT_AON_PTC0_PWM7 6 264 #define GPOUT_AON_CLK_GCLK0 7 265 #define GPOUT_AON_CLK_GCLK1 8 266 #define GPOUT_AON_CLK_GCLK2 9 267 268 /* sys_iomux doen */ 269 #define GPOEN_ENABLE 0 270 #define GPOEN_DISABLE 1 271 #define GPOEN_SYS_HDMI_CEC_SDA 2 272 #define GPOEN_SYS_HDMI_DDC_SCL 3 273 #define GPOEN_SYS_HDMI_DDC_SDA 4 274 #define GPOEN_SYS_I2C0_CLK 5 275 #define GPOEN_SYS_I2C0_DATA 6 276 #define GPOEN_SYS_HIFI4_JTAG_TDO 7 277 #define GPOEN_SYS_JTAG_TDO 8 278 #define GPOEN_SYS_PWM0_CHANNEL0 9 279 #define GPOEN_SYS_PWM0_CHANNEL1 10 280 #define GPOEN_SYS_PWM0_CHANNEL2 11 281 #define GPOEN_SYS_PWM0_CHANNEL3 12 282 #define GPOEN_SYS_SPI0_NSSPCTL 13 283 #define GPOEN_SYS_SPI0_NSSP 14 284 #define GPOEN_SYS_TDM_SYNC 15 285 #define GPOEN_SYS_TDM_TXD 16 286 #define GPOEN_SYS_I2C1_CLK 17 287 #define GPOEN_SYS_I2C1_DATA 18 288 #define GPOEN_SYS_SDIO1_CMD 19 289 #define GPOEN_SYS_SDIO1_DATA0 20 290 #define GPOEN_SYS_SDIO1_DATA1 21 291 #define GPOEN_SYS_SDIO1_DATA2 22 292 #define GPOEN_SYS_SDIO1_DATA3 23 293 #define GPOEN_SYS_SDIO1_DATA4 24 294 #define GPOEN_SYS_SDIO1_DATA5 25 295 #define GPOEN_SYS_SDIO1_DATA6 26 296 #define GPOEN_SYS_SDIO1_DATA7 27 297 #define GPOEN_SYS_SPI1_NSSPCTL 28 298 #define GPOEN_SYS_SPI1_NSSP 29 299 #define GPOEN_SYS_I2C2_CLK 30 300 #define GPOEN_SYS_I2C2_DATA 31 301 #define GPOEN_SYS_SPI2_NSSPCTL 32 302 #define GPOEN_SYS_SPI2_NSSP 33 303 #define GPOEN_SYS_I2C3_CLK 34 304 #define GPOEN_SYS_I2C3_DATA 35 305 #define GPOEN_SYS_SPI3_NSSPCTL 36 306 #define GPOEN_SYS_SPI3_NSSP 37 307 #define GPOEN_SYS_I2C4_CLK 38 308 #define GPOEN_SYS_I2C4_DATA 39 309 #define GPOEN_SYS_SPI4_NSSPCTL 40 310 #define GPOEN_SYS_SPI4_NSSP 41 311 #define GPOEN_SYS_I2C5_CLK 42 312 #define GPOEN_SYS_I2C5_DATA 43 313 #define GPOEN_SYS_SPI5_NSSPCTL 44 314 #define GPOEN_SYS_SPI5_NSSP 45 315 #define GPOEN_SYS_I2C6_CLK 46 316 #define GPOEN_SYS_I2C6_DATA 47 317 #define GPOEN_SYS_SPI6_NSSPCTL 48 318 #define GPOEN_SYS_SPI6_NSSP 49 319 320 /* aon_iomux doen */ 321 #define GPOEN_AON_PTC0_OE_N_4 2 322 #define GPOEN_AON_PTC0_OE_N_5 3 323 #define GPOEN_AON_PTC0_OE_N_6 4 324 #define GPOEN_AON_PTC0_OE_N_7 5 325 326 /* sys_iomux gin */ 327 #define GPI_NONE 255 328 329 #define GPI_SYS_WAVE511_UART_RX 0 330 #define GPI_SYS_CAN0_RXD 1 331 #define GPI_SYS_USB_OVERCURRENT 2 332 #define GPI_SYS_SPDIF 3 333 #define GPI_SYS_JTAG_RST 4 334 #define GPI_SYS_HDMI_CEC_SDA 5 335 #define GPI_SYS_HDMI_DDC_SCL 6 336 #define GPI_SYS_HDMI_DDC_SDA 7 337 #define GPI_SYS_HDMI_HPD 8 338 #define GPI_SYS_I2C0_CLK 9 339 #define GPI_SYS_I2C0_DATA 10 340 #define GPI_SYS_SDIO0_CD 11 341 #define GPI_SYS_SDIO0_INT 12 342 #define GPI_SYS_SDIO0_WP 13 343 #define GPI_SYS_UART0_RX 14 344 #define GPI_SYS_HIFI4_JTAG_TCK 15 345 #define GPI_SYS_HIFI4_JTAG_TDI 16 346 #define GPI_SYS_HIFI4_JTAG_TMS 17 347 #define GPI_SYS_HIFI4_JTAG_RST 18 348 #define GPI_SYS_JTAG_TDI 19 349 #define GPI_SYS_JTAG_TMS 20 350 #define GPI_SYS_PDM_DMIC0 21 351 #define GPI_SYS_PDM_DMIC1 22 352 #define GPI_SYS_I2SRX_SDIN0 23 353 #define GPI_SYS_I2SRX_SDIN1 24 354 #define GPI_SYS_I2SRX_SDIN2 25 355 #define GPI_SYS_SPI0_CLK 26 356 #define GPI_SYS_SPI0_FSS 27 357 #define GPI_SYS_SPI0_RXD 28 358 #define GPI_SYS_JTAG_TCK 29 359 #define GPI_SYS_MCLK_EXT 30 360 #define GPI_SYS_I2SRX_BCLK 31 361 #define GPI_SYS_I2SRX_LRCK 32 362 #define GPI_SYS_I2STX0_BCLK 33 363 #define GPI_SYS_I2STX0_LRCK 34 364 #define GPI_SYS_TDM_CLK 35 365 #define GPI_SYS_TDM_RXD 36 366 #define GPI_SYS_TDM_SYNC 37 367 #define GPI_SYS_CAN1_RXD 38 368 #define GPI_SYS_I2C1_CLK 39 369 #define GPI_SYS_I2C1_DATA 40 370 #define GPI_SYS_SDIO1_CD 41 371 #define GPI_SYS_SDIO1_INT 42 372 #define GPI_SYS_SDIO1_WP 43 373 #define GPI_SYS_SDIO1_CMD 44 374 #define GPI_SYS_SDIO1_DATA0 45 375 #define GPI_SYS_SDIO1_DATA1 46 376 #define GPI_SYS_SDIO1_DATA2 47 377 #define GPI_SYS_SDIO1_DATA3 48 378 #define GPI_SYS_SDIO1_DATA4 49 379 #define GPI_SYS_SDIO1_DATA5 50 380 #define GPI_SYS_SDIO1_DATA6 51 381 #define GPI_SYS_SDIO1_DATA7 52 382 #define GPI_SYS_SDIO1_STRB 53 383 #define GPI_SYS_UART1_CTS 54 384 #define GPI_SYS_UART1_RX 55 385 #define GPI_SYS_SPI1_CLK 56 386 #define GPI_SYS_SPI1_FSS 57 387 #define GPI_SYS_SPI1_RXD 58 388 #define GPI_SYS_I2C2_CLK 59 389 #define GPI_SYS_I2C2_DATA 60 390 #define GPI_SYS_UART2_CTS 61 391 #define GPI_SYS_UART2_RX 62 392 #define GPI_SYS_SPI2_CLK 63 393 #define GPI_SYS_SPI2_FSS 64 394 #define GPI_SYS_SPI2_RXD 65 395 #define GPI_SYS_I2C3_CLK 66 396 #define GPI_SYS_I2C3_DATA 67 397 #define GPI_SYS_UART3_RX 68 398 #define GPI_SYS_SPI3_CLK 69 399 #define GPI_SYS_SPI3_FSS 70 400 #define GPI_SYS_SPI3_RXD 71 401 #define GPI_SYS_I2C4_CLK 72 402 #define GPI_SYS_I2C4_DATA 73 403 #define GPI_SYS_UART4_CTS 74 404 #define GPI_SYS_UART4_RX 75 405 #define GPI_SYS_SPI4_CLK 76 406 #define GPI_SYS_SPI4_FSS 77 407 #define GPI_SYS_SPI4_RXD 78 408 #define GPI_SYS_I2C5_CLK 79 409 #define GPI_SYS_I2C5_DATA 80 410 #define GPI_SYS_UART5_CTS 81 411 #define GPI_SYS_UART5_RX 82 412 #define GPI_SYS_SPI5_CLK 83 413 #define GPI_SYS_SPI5_FSS 84 414 #define GPI_SYS_SPI5_RXD 85 415 #define GPI_SYS_I2C6_CLK 86 416 #define GPI_SYS_I2C6_DATA 87 417 #define GPI_SYS_SPI6_CLK 88 418 #define GPI_SYS_SPI6_FSS 89 419 #define GPI_SYS_SPI6_RXD 90 420 421 /* aon_iomux gin */ 422 #define GPI_AON_PMU_GPIO_WAKEUP_0 0 423 #define GPI_AON_PMU_GPIO_WAKEUP_1 1 424 #define GPI_AON_PMU_GPIO_WAKEUP_2 2 425 #define GPI_AON_PMU_GPIO_WAKEUP_3 3 426 427 #endif 428