1 /* 2 * Marvell MBUS common definitions. 3 * 4 * Copyright (C) 2008 Marvell Semiconductor 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __LINUX_MBUS_H 12 #define __LINUX_MBUS_H 13 14 struct resource; 15 16 struct mbus_dram_target_info { 17 /* 18 * The 4-bit MBUS target ID of the DRAM controller. 19 */ 20 u8 mbus_dram_target_id; 21 22 /* 23 * The base address, size, and MBUS attribute ID for each 24 * of the possible DRAM chip selects. Peripherals are 25 * required to support at least 4 decode windows. 26 */ 27 int num_cs; 28 struct mbus_dram_window { 29 u8 cs_index; 30 u8 mbus_attr; 31 u32 base; 32 u32 size; 33 } cs[4]; 34 }; 35 36 /* Flags for PCI/PCIe address decoding regions */ 37 #define MVEBU_MBUS_PCI_IO 0x1 38 #define MVEBU_MBUS_PCI_MEM 0x2 39 #define MVEBU_MBUS_PCI_WA 0x3 40 41 /* 42 * Magic value that explicits that we don't need a remapping-capable 43 * address decoding window. 44 */ 45 #define MVEBU_MBUS_NO_REMAP (0xffffffff) 46 47 /* Maximum size of a mbus window name */ 48 #define MVEBU_MBUS_MAX_WINNAME_SZ 32 49 50 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void); 51 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); 52 void mvebu_mbus_get_pcie_io_aperture(struct resource *res); 53 int mvebu_mbus_add_window_remap_by_id(unsigned int target, 54 unsigned int attribute, 55 phys_addr_t base, size_t size, 56 phys_addr_t remap); 57 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, 58 phys_addr_t base, size_t size); 59 int mvebu_mbus_del_window(phys_addr_t base, size_t size); 60 int mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr); 61 62 #endif /* __LINUX_MBUS_H */ 63