Lines Matching refs:DDR_Cmd
300 static void DDR_Cmd(const uint32_t cmd ,const uint32_t param) in DDR_Cmd() function
307 DDR_Cmd(SW_CMD_NOP,cycle); in DDR_Latency()
340 DDR_Cmd(SW_CMD_NOPCKE,(PRE_ALL_NOP/period)); in DDR2_conf()
341 DDR_Cmd(SW_CMD_PREA,NULL); in DDR2_conf()
343 DDR_Cmd(SW_CMD_EMR2,NULL); in DDR2_conf()
345 DDR_Cmd(SW_CMD_EMR3,NULL); in DDR2_conf()
347 DDR_Cmd(SW_CMD_DLL_EN,NULL); in DDR2_conf()
349 DDR_Cmd(SW_CMD_DLL_RST,NULL); in DDR2_conf()
351 DDR_Cmd(SW_CMD_PREA,NULL); in DDR2_conf()
353 DDR_Cmd(SW_CMD_REF,NULL); in DDR2_conf()
355 DDR_Cmd(SW_CMD_REF,NULL); in DDR2_conf()
357 DDR_Cmd(SW_CMD_MR,(((ptr->tWR-1)<<MR_WR_OFFSET)|(ptr->tCL<<MR_CL_OFFSET)|MR_BURST_LEN_8)); in DDR2_conf()
359 DDR_Cmd(SW_CMD_EMR1_TEST,NULL); in DDR2_conf()
397 DDR_Cmd(SW_CMD_RSTH,NULL);// RESET H in DDR3_conf()
399 …DDR_Cmd(SW_CMD_NOPCKE,((tRFC+10)/period));// cke high 170/tck tck txpr max(5nck, trfc(min) + 1… in DDR3_conf()
400 DDR_Cmd(SW_CMD_EMR2,((ptr->tWCL-5)<<MR2_CWL_OFFSET)); //MR2 in DDR3_conf()
402 DDR_Cmd(SW_CMD_EMR3,NULL);// MR3 in DDR3_conf()
404 DDR_Cmd(SW_CMD_EMR1,MR1_RZQ_4); // MR1 in DDR3_conf()
406 … DDR_Cmd(SW_CMD_MR,(MR_PPD_FAST|MR_DLL_YES|((ptr->tWR-1)<<MR_WR_OFFSET)|(CAL_DDR3_CL(ptr->tCL)))); in DDR3_conf()
418 DDR_Cmd(SW_CMD_ZQCL,NULL);// ZQCL starting ZQ calibration in DDR3_conf()