Lines Matching refs:PHY_ADDR
136 #define PHY_ADDR (0) /* Value depends on PHY and its hardware configurations */ macro
676 …Cy_ETHIF_PhyRegWrite(reg_base, 0x1F, 0x8000, PHY_ADDR); /* Ext-Reg CTRl: Perform a full reset, inc… in init_phy_DP83867IR()
736 …Cy_ETHIF_PhyRegWrite(reg_base, 0x10, 0x5028, PHY_ADDR); /** Disable auto negotiation for MDI/MDI-X… in enable_phy_DP83867IR_extended_reg()
741 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x001F, PHY_ADDR); /** Begin write access to the exte… in enable_phy_DP83867IR_extended_reg()
742 Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0170, PHY_ADDR); in enable_phy_DP83867IR_extended_reg()
743 Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x401F, PHY_ADDR); in enable_phy_DP83867IR_extended_reg()
744 u32ReadData = Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x0E, PHY_ADDR); in enable_phy_DP83867IR_extended_reg()
747 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, u32ReadData, PHY_ADDR); /** Enable clock from the PHY… in enable_phy_DP83867IR_extended_reg()
748 u32ReadData = Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x0E, PHY_ADDR); in enable_phy_DP83867IR_extended_reg()
756 Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x001F, PHY_ADDR); /** REGCR */ in enable_phy_DP83867IR_extended_reg()
757 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0032, PHY_ADDR); /** ADDAR, 0x0032 RGMI… in enable_phy_DP83867IR_extended_reg()
758 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x401F, PHY_ADDR); /** REGCR; will force … in enable_phy_DP83867IR_extended_reg()
762 … Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0000, PHY_ADDR); /** Disable RGMII */ in enable_phy_DP83867IR_extended_reg()
763 Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x0E, PHY_ADDR); /** Read RGMII mode status */ in enable_phy_DP83867IR_extended_reg()
767 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x00D3, PHY_ADDR); /** Enable Tx and RX c… in enable_phy_DP83867IR_extended_reg()
769 Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x001F, PHY_ADDR); /** REGCR */ in enable_phy_DP83867IR_extended_reg()
770 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0086, PHY_ADDR); /** ADDAR; 0x0086 dela… in enable_phy_DP83867IR_extended_reg()
771 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x401F, PHY_ADDR); /** REGCR; will force … in enable_phy_DP83867IR_extended_reg()
772 …Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0066, PHY_ADDR); /** Adjust Tx and Rx c… in enable_phy_DP83867IR_extended_reg()
775 Cy_ETHIF_PhyRegWrite(reg_base, 0x1F, 0x4000, PHY_ADDR); /** CTRL */ in enable_phy_DP83867IR_extended_reg()
777 Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x11, PHY_ADDR); in enable_phy_DP83867IR_extended_reg()