Lines Matching refs:ui32PwrStatDisMask

206     uint32_t ui32PwrStatEnMask, ui32PwrStatDisMask;  in am_hal_pwrctrl_memory_enable()  local
214 ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M; in am_hal_pwrctrl_memory_enable()
223 ui32PwrStatDisMask = 0; in am_hal_pwrctrl_memory_enable()
231 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
240 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
253 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
262 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
271 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
280 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
289 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
298 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
307 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
316 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
325 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & in am_hal_pwrctrl_memory_enable()
335 ui32PwrStatDisMask = 0; in am_hal_pwrctrl_memory_enable()
343 ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M | in am_hal_pwrctrl_memory_enable()
351 ui32PwrStatDisMask = 0; in am_hal_pwrctrl_memory_enable()
383 if ( ui32PwrStatDisMask ) in am_hal_pwrctrl_memory_enable()
386 ( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatDisMask ) ); in am_hal_pwrctrl_memory_enable()