Lines Matching refs:ui32PwrStatEnMask
206 uint32_t ui32PwrStatEnMask, ui32PwrStatDisMask; in am_hal_pwrctrl_memory_enable() local
213 ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M; in am_hal_pwrctrl_memory_enable()
221 ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M | in am_hal_pwrctrl_memory_enable()
230 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K; in am_hal_pwrctrl_memory_enable()
239 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K; in am_hal_pwrctrl_memory_enable()
252 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K; in am_hal_pwrctrl_memory_enable()
261 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K; in am_hal_pwrctrl_memory_enable()
270 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K; in am_hal_pwrctrl_memory_enable()
279 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K; in am_hal_pwrctrl_memory_enable()
288 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K; in am_hal_pwrctrl_memory_enable()
297 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K; in am_hal_pwrctrl_memory_enable()
306 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K; in am_hal_pwrctrl_memory_enable()
315 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K; in am_hal_pwrctrl_memory_enable()
324 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K; in am_hal_pwrctrl_memory_enable()
333 ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M | in am_hal_pwrctrl_memory_enable()
342 ui32PwrStatEnMask = 0; in am_hal_pwrctrl_memory_enable()
350 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL; in am_hal_pwrctrl_memory_enable()
395 if ( ui32PwrStatEnMask ) in am_hal_pwrctrl_memory_enable()
398 (( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatEnMask ) in am_hal_pwrctrl_memory_enable()
399 != ui32PwrStatEnMask) ); in am_hal_pwrctrl_memory_enable()