Lines Matching refs:prcm_base
231 unsigned long prcm_base; in poweron_per_domain() local
234 prcm_base = AM33XX_PRCM_REGS; in poweron_per_domain()
237 for (prm_state = PRM_PER_PWRSTST_REG(prcm_base); in poweron_per_domain()
239 prm_state = PRM_PER_PWRSTST_REG(prcm_base)) in poweron_per_domain()
245 PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3; in poweron_per_domain()
250 PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3 << 25; in poweron_per_domain()
252 while (PRM_PER_PWRSTST_REG(prcm_base) & PRM_PER_INTRANSLATION) in poweron_per_domain()
258 unsigned long prcm_base; in start_uart_clk() local
260 prcm_base = AM33XX_PRCM_REGS; in start_uart_clk()
264 CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
267 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8))) in start_uart_clk()
272 CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
274 while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) in start_uart_clk()
279 CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
281 while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) in start_uart_clk()
286 CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
288 while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) in start_uart_clk()
293 CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
295 while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) in start_uart_clk()
300 CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
302 while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) in start_uart_clk()
307 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10))) in start_uart_clk()
313 CM_WKUP_CLKSTCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
316 while (!(CM_WKUP_CLKSTCTRL_REG(prcm_base) & (1<<2))) in start_uart_clk()
320 CM_WKUP_UART0_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()
322 while ((CM_WKUP_UART0_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) in start_uart_clk()
326 while (!(CM_WKUP_CLKSTCTRL_REG(prcm_base) & (1<<12))) in start_uart_clk()