Lines Matching refs:rtc_base
108 static void hal_cvi_rtc_enable_sec_counter(uintptr_t rtc_base) in hal_cvi_rtc_enable_sec_counter() argument
112 value = mmio_read_32(rtc_base + CVI_RTC_SEC_PULSE_GEN) & 0x7FFFFFFF; in hal_cvi_rtc_enable_sec_counter()
113 mmio_write_32(rtc_base + CVI_RTC_SEC_PULSE_GEN, value); in hal_cvi_rtc_enable_sec_counter()
115 value = mmio_read_32(rtc_base + CVI_RTC_ANA_CALIB) & 0x7FFFFFFF; in hal_cvi_rtc_enable_sec_counter()
116 mmio_write_32(rtc_base + CVI_RTC_ANA_CALIB, value); in hal_cvi_rtc_enable_sec_counter()
118 mmio_read_32(rtc_base + CVI_RTC_SEC_CNTR_VALUE); in hal_cvi_rtc_enable_sec_counter()
119 mmio_write_32(rtc_base + CVI_RTC_ALARM_ENABLE, 0x0); in hal_cvi_rtc_enable_sec_counter()
122 static void hal_cvi_rtc_set_time(uintptr_t rtc_base, unsigned long sec) in hal_cvi_rtc_set_time() argument
124 mmio_write_32(rtc_base + CVI_RTC_SET_SEC_CNTR_VALUE, sec); in hal_cvi_rtc_set_time()
125 mmio_write_32(rtc_base + CVI_RTC_SET_SEC_CNTR_TRIG, 1); in hal_cvi_rtc_set_time()
126 mmio_write_32(rtc_base + RTC_MACRO_RG_SET_T, sec); in hal_cvi_rtc_set_time()
127 mmio_write_32(rtc_base + RTC_MACRO_DA_CLEAR_ALL, 1); in hal_cvi_rtc_set_time()
128 mmio_write_32(rtc_base + RTC_MACRO_DA_SOC_READY, 1); in hal_cvi_rtc_set_time()
129 mmio_write_32(rtc_base + RTC_MACRO_DA_CLEAR_ALL, 0); in hal_cvi_rtc_set_time()
130 mmio_write_32(rtc_base + RTC_MACRO_RG_SET_T, 0); in hal_cvi_rtc_set_time()
131 mmio_write_32(rtc_base + RTC_MACRO_DA_SOC_READY, 0); in hal_cvi_rtc_set_time()
134 static int hal_cvi_rtc_get_time_sec(uintptr_t rtc_base,unsigned long *ret_sec) in hal_cvi_rtc_get_time_sec() argument
140 sec = mmio_read_32(rtc_base + CVI_RTC_SEC_CNTR_VALUE); in hal_cvi_rtc_get_time_sec()
141 sec_ro_t = mmio_read_32(rtc_base + RTC_MACRO_RO_T); in hal_cvi_rtc_get_time_sec()
148 mmio_write_32(rtc_base + CVI_RTC_SET_SEC_CNTR_VALUE, sec); in hal_cvi_rtc_get_time_sec()
149 mmio_write_32(rtc_base + CVI_RTC_SET_SEC_CNTR_TRIG, 1); in hal_cvi_rtc_get_time_sec()