Lines Matching refs:edma_shadow0_write_array
174 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, in edma_shadow0_write_array() function
398 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, in setup_dma_interrupt()
405 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, in setup_dma_interrupt()
407 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, in setup_dma_interrupt()
462 edma_shadow0_write_array(ctlr, SH_ICR, j, in dma_irq_handler()
519 edma_shadow0_write_array(ctlr, SH_SECR, in dma_ccerr_handler()
1300 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); in edma_pause()
1321 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); in edma_resume()
1352 edma_shadow0_write_array(ctlr, SH_ESR, j, mask); in edma_start()
1363 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_start()
1364 edma_shadow0_write_array(ctlr, SH_EESR, j, mask); in edma_start()
1394 edma_shadow0_write_array(ctlr, SH_EECR, j, mask); in edma_stop()
1395 edma_shadow0_write_array(ctlr, SH_ECR, j, mask); in edma_stop()
1396 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_stop()
1435 edma_shadow0_write_array(ctlr, SH_ECR, j, mask); in edma_clean_channel()
1439 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_clean_channel()