Lines Matching refs:enCh
259 en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig) in Dma_InitChannel() argument
261 ASSERT(IS_VALID_CH(enCh)); in Dma_InitChannel()
270 if (!IS_VALID_CH(enCh)) in Dma_InitChannel()
274 if(enCh == DmaCh0) in Dma_InitChannel()
372 void Dma_SwTrigger(en_dma_channel_t enCh) in Dma_SwTrigger() argument
374 ASSERT(IS_VALID_CH(enCh)); in Dma_SwTrigger()
375 if(enCh == DmaCh0) in Dma_SwTrigger()
426 void Dma_Start(en_dma_channel_t enCh) in Dma_Start() argument
428 ASSERT(IS_VALID_CH(enCh)); in Dma_Start()
429 if(enCh == DmaCh0) in Dma_Start()
449 void Dma_Stop(en_dma_channel_t enCh) in Dma_Stop() argument
451 ASSERT(IS_VALID_CH(enCh)); in Dma_Stop()
452 if(enCh == DmaCh0) in Dma_Stop()
477 en_result_t Dma_EnableIrq(en_dma_channel_t enCh, stc_dma_irq_sel_t stcIrqSel) in Dma_EnableIrq() argument
481 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableIrq()
483 if(!IS_VALID_CH(enCh)) in Dma_EnableIrq()
490 Dma_EnableChannelIrq(enCh); in Dma_EnableIrq()
494 Dma_EnableChannelErrIrq(enCh); in Dma_EnableIrq()
517 en_result_t Dma_DisableIrq(en_dma_channel_t enCh, stc_dma_irq_sel_t stcIrqSel) in Dma_DisableIrq() argument
521 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableIrq()
523 if(!IS_VALID_CH(enCh)) in Dma_DisableIrq()
530 Dma_DisableChannelIrq(enCh); in Dma_DisableIrq()
534 Dma_DisableChannelErrIrq(enCh); in Dma_DisableIrq()
552 en_result_t Dma_EnableChannel(en_dma_channel_t enCh) in Dma_EnableChannel() argument
554 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableChannel()
556 if(!IS_VALID_CH(enCh)) in Dma_EnableChannel()
561 if(enCh == DmaCh0) in Dma_EnableChannel()
584 en_result_t Dma_DisableChannel(en_dma_channel_t enCh) in Dma_DisableChannel() argument
586 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableChannel()
588 if(!IS_VALID_CH(enCh)) in Dma_DisableChannel()
593 if(enCh == DmaCh0) in Dma_DisableChannel()
617 en_result_t Dma_SetTriggerSel(en_dma_channel_t enCh, en_dma_trig_sel_t enTrgSel) in Dma_SetTriggerSel() argument
619 ASSERT(IS_VALID_CH(enCh)); in Dma_SetTriggerSel()
621 if(!IS_VALID_CH(enCh)) in Dma_SetTriggerSel()
626 if(enCh == DmaCh0) in Dma_SetTriggerSel()
650 en_result_t Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address) in Dma_SetSourceAddress() argument
652 ASSERT(IS_VALID_CH(enCh)); in Dma_SetSourceAddress()
654 if(!IS_VALID_CH(enCh)) in Dma_SetSourceAddress()
659 if(enCh == DmaCh0) in Dma_SetSourceAddress()
684 en_result_t Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address) in Dma_SetDestinationAddress() argument
686 ASSERT(IS_VALID_CH(enCh)); in Dma_SetDestinationAddress()
688 if(!IS_VALID_CH(enCh)) in Dma_SetDestinationAddress()
693 if(enCh == DmaCh0) in Dma_SetDestinationAddress()
718 en_result_t Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize) in Dma_SetBlockSize() argument
720 ASSERT(IS_VALID_CH(enCh)); in Dma_SetBlockSize()
723 if((!IS_VALID_CH(enCh)) || (!IS_VALID_BLKSIZE(u16BlkSize))) in Dma_SetBlockSize()
728 if(enCh == DmaCh0) in Dma_SetBlockSize()
752 en_result_t Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt) in Dma_SetTransferCnt() argument
754 ASSERT(IS_VALID_CH(enCh)); in Dma_SetTransferCnt()
757 if((!IS_VALID_CH(enCh)) || (!IS_VALID_TRNCNT(u16TrnCnt))) in Dma_SetTransferCnt()
762 if(enCh == DmaCh0) in Dma_SetTransferCnt()
787 en_result_t Dma_EnableSourceRload(en_dma_channel_t enCh) in Dma_EnableSourceRload() argument
789 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableSourceRload()
791 if((!IS_VALID_CH(enCh))) in Dma_EnableSourceRload()
795 if(enCh == DmaCh0) in Dma_EnableSourceRload()
820 en_result_t Dma_DisableSourceRload(en_dma_channel_t enCh) in Dma_DisableSourceRload() argument
822 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableSourceRload()
824 if(!IS_VALID_CH(enCh)) in Dma_DisableSourceRload()
829 if(enCh == DmaCh0) in Dma_DisableSourceRload()
853 en_result_t Dma_EnableDestinationRload(en_dma_channel_t enCh) in Dma_EnableDestinationRload() argument
855 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableDestinationRload()
857 if((!IS_VALID_CH(enCh))) in Dma_EnableDestinationRload()
861 if(enCh == DmaCh0) in Dma_EnableDestinationRload()
885 en_result_t Dma_DisableDestinationRload(en_dma_channel_t enCh) in Dma_DisableDestinationRload() argument
887 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableDestinationRload()
889 if(!IS_VALID_CH(enCh)) in Dma_DisableDestinationRload()
894 if(enCh == DmaCh0) in Dma_DisableDestinationRload()
917 en_result_t Dma_EnableBcTcReload(en_dma_channel_t enCh) in Dma_EnableBcTcReload() argument
919 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableBcTcReload()
921 if((!IS_VALID_CH(enCh))) in Dma_EnableBcTcReload()
925 if(enCh == DmaCh0) in Dma_EnableBcTcReload()
949 en_result_t Dma_DisableBcTcReload(en_dma_channel_t enCh) in Dma_DisableBcTcReload() argument
951 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableBcTcReload()
953 if(!IS_VALID_CH(enCh)) in Dma_DisableBcTcReload()
958 if(enCh == DmaCh0) in Dma_DisableBcTcReload()
984 en_result_t Dma_SetSourceIncMode(en_dma_channel_t enCh, en_address_mode_t enMode) in Dma_SetSourceIncMode() argument
986 ASSERT(IS_VALID_CH(enCh)); in Dma_SetSourceIncMode()
989 if((!IS_VALID_CH(enCh)) || (!IS_VALID_ADDR_MODE(enMode))) in Dma_SetSourceIncMode()
994 if(enCh == DmaCh0) in Dma_SetSourceIncMode()
1022 en_result_t Dma_SetDestinationIncMode(en_dma_channel_t enCh, en_address_mode_t enMode) in Dma_SetDestinationIncMode() argument
1024 ASSERT(IS_VALID_CH(enCh)); in Dma_SetDestinationIncMode()
1027 if((!IS_VALID_CH(enCh)) || (!IS_VALID_ADDR_MODE(enMode))) in Dma_SetDestinationIncMode()
1032 if(enCh == DmaCh0) in Dma_SetDestinationIncMode()
1055 en_result_t Dma_EnableContinusTranfer(en_dma_channel_t enCh) in Dma_EnableContinusTranfer() argument
1057 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableContinusTranfer()
1059 if(!IS_VALID_CH(enCh)) in Dma_EnableContinusTranfer()
1063 if(enCh == DmaCh0) in Dma_EnableContinusTranfer()
1085 en_result_t Dma_DisableContinusTranfer(en_dma_channel_t enCh) in Dma_DisableContinusTranfer() argument
1087 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableContinusTranfer()
1089 if(!IS_VALID_CH(enCh)) in Dma_DisableContinusTranfer()
1094 if(enCh == DmaCh0) in Dma_DisableContinusTranfer()
1148 en_result_t Dma_PauseChannelTranfer(en_dma_channel_t enCh) in Dma_PauseChannelTranfer() argument
1150 ASSERT(IS_VALID_CH(enCh)); in Dma_PauseChannelTranfer()
1152 if((!IS_VALID_CH(enCh))) in Dma_PauseChannelTranfer()
1157 if(enCh == DmaCh0) in Dma_PauseChannelTranfer()
1178 en_result_t Dma_RecoverChannelTranfer(en_dma_channel_t enCh) in Dma_RecoverChannelTranfer() argument
1180 ASSERT(IS_VALID_CH(enCh)); in Dma_RecoverChannelTranfer()
1182 if((!IS_VALID_CH(enCh))) in Dma_RecoverChannelTranfer()
1187 if(enCh == DmaCh0) in Dma_RecoverChannelTranfer()
1212 en_result_t Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth) in Dma_SetTransferWidth() argument
1214 ASSERT(IS_VALID_CH(enCh)); in Dma_SetTransferWidth()
1217 if((!IS_VALID_CH(enCh)) || (!IS_VALID_TRN_WIDTH(enWidth))) in Dma_SetTransferWidth()
1222 if(enCh == DmaCh0) in Dma_SetTransferWidth()
1272 en_result_t Dma_EnableChannelIrq(en_dma_channel_t enCh) in Dma_EnableChannelIrq() argument
1274 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableChannelIrq()
1276 if(!IS_VALID_CH(enCh)) in Dma_EnableChannelIrq()
1280 if(enCh == DmaCh0) in Dma_EnableChannelIrq()
1303 en_result_t Dma_DisableChannelIrq(en_dma_channel_t enCh) in Dma_DisableChannelIrq() argument
1305 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableChannelIrq()
1307 if(!IS_VALID_CH(enCh)) in Dma_DisableChannelIrq()
1311 if(enCh == DmaCh0) in Dma_DisableChannelIrq()
1333 en_result_t Dma_EnableChannelErrIrq(en_dma_channel_t enCh) in Dma_EnableChannelErrIrq() argument
1335 ASSERT(IS_VALID_CH(enCh)); in Dma_EnableChannelErrIrq()
1337 if(!IS_VALID_CH(enCh)) in Dma_EnableChannelErrIrq()
1341 if(enCh == DmaCh0) in Dma_EnableChannelErrIrq()
1364 en_result_t Dma_DisableChannelErrIrq(en_dma_channel_t enCh) in Dma_DisableChannelErrIrq() argument
1366 ASSERT(IS_VALID_CH(enCh)); in Dma_DisableChannelErrIrq()
1368 if(!IS_VALID_CH(enCh)) in Dma_DisableChannelErrIrq()
1372 if(enCh == DmaCh0) in Dma_DisableChannelErrIrq()
1437 en_result_t Dma_ConfigIrq(en_dma_channel_t enCh,stc_dma_irq_sel_t* stcDmaIrqCfg,stc_dma_irq_calbakf… in Dma_ConfigIrq() argument
1439 ASSERT(IS_VALID_CH(enCh)); in Dma_ConfigIrq()
1441 if(!IS_VALID_CH(enCh)) in Dma_ConfigIrq()
1445 if(DmaCh0 == enCh) in Dma_ConfigIrq()
1462 else if(DmaCh1 == enCh) in Dma_ConfigIrq()
1493 en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh) in Dma_GetStat() argument
1495 ASSERT(IS_VALID_CH(enCh)); in Dma_GetStat()
1497 if(!IS_VALID_CH(enCh)) in Dma_GetStat()
1501 if(enCh == DmaCh0) in Dma_GetStat()
1520 void Dma_ClrStat(en_dma_channel_t enCh) in Dma_ClrStat() argument
1522 ASSERT(IS_VALID_CH(enCh)); in Dma_ClrStat()
1524 if(enCh == DmaCh0) in Dma_ClrStat()