Lines Matching refs:ulBase
87 ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, in ADCIntRegister() argument
95 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntRegister()
101 ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) : in ADCIntRegister()
133 ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) in ADCIntUnregister() argument
140 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntUnregister()
146 ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) : in ADCIntUnregister()
173 ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) in ADCIntDisable() argument
178 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntDisable()
184 HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); in ADCIntDisable()
202 ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) in ADCIntEnable() argument
207 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntEnable()
213 HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; in ADCIntEnable()
218 HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; in ADCIntEnable()
238 ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, in ADCIntStatus() argument
246 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntStatus()
255 ulTemp = HWREG(ulBase + ADC_O_ISC) & (0x10001 << ulSequenceNum); in ADCIntStatus()
259 ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum)); in ADCIntStatus()
302 ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) in ADCIntClear() argument
307 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntClear()
313 HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; in ADCIntClear()
330 ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) in ADCSequenceEnable() argument
335 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceEnable()
341 HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; in ADCSequenceEnable()
358 ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) in ADCSequenceDisable() argument
363 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceDisable()
369 HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); in ADCSequenceDisable()
430 ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, in ADCSequenceConfigure() argument
436 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceConfigure()
459 HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & in ADCSequenceConfigure()
466 HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & in ADCSequenceConfigure()
522 ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, in ADCSequenceStepConfigure() argument
530 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceStepConfigure()
540 ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); in ADCSequenceStepConfigure()
550 HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & in ADCSequenceStepConfigure()
557 HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & in ADCSequenceStepConfigure()
564 HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & in ADCSequenceStepConfigure()
576 ulTemp = HWREG(ulBase + ADC_SSDC); in ADCSequenceStepConfigure()
579 HWREG(ulBase + ADC_SSDC) = ulTemp; in ADCSequenceStepConfigure()
584 ulTemp = HWREG(ulBase + ADC_SSOP); in ADCSequenceStepConfigure()
586 HWREG(ulBase + ADC_SSOP) = ulTemp; in ADCSequenceStepConfigure()
594 ulTemp = HWREG(ulBase + ADC_SSOP); in ADCSequenceStepConfigure()
596 HWREG(ulBase + ADC_SSOP) = ulTemp; in ADCSequenceStepConfigure()
616 ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) in ADCSequenceOverflow() argument
621 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceOverflow()
627 return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); in ADCSequenceOverflow()
645 ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum) in ADCSequenceOverflowClear() argument
650 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceOverflowClear()
656 HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum; in ADCSequenceOverflowClear()
674 ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) in ADCSequenceUnderflow() argument
679 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceUnderflow()
685 return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); in ADCSequenceUnderflow()
703 ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum) in ADCSequenceUnderflowClear() argument
708 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceUnderflowClear()
714 HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum; in ADCSequenceUnderflowClear()
736 ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, in ADCSequenceDataGet() argument
744 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceDataGet()
750 ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); in ADCSequenceDataGet()
756 while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8)) in ADCSequenceDataGet()
761 *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO); in ADCSequenceDataGet()
795 ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) in ADCProcessorTrigger() argument
800 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCProcessorTrigger()
806 HWREG(ulBase + ADC_O_PSSI) |= ((ulSequenceNum & 0xffff0000) | in ADCProcessorTrigger()
834 ADCSoftwareOversampleConfigure(unsigned long ulBase, in ADCSoftwareOversampleConfigure() argument
843 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSoftwareOversampleConfigure()
879 ADCSoftwareOversampleStepConfigure(unsigned long ulBase, in ADCSoftwareOversampleStepConfigure() argument
887 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSoftwareOversampleStepConfigure()
896 ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); in ADCSoftwareOversampleStepConfigure()
913 HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & in ADCSoftwareOversampleStepConfigure()
920 HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) & in ADCSoftwareOversampleStepConfigure()
927 HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & in ADCSoftwareOversampleStepConfigure()
932 HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 | in ADCSoftwareOversampleStepConfigure()
964 ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, in ADCSoftwareOversampleDataGet() argument
972 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSoftwareOversampleDataGet()
981 ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); in ADCSoftwareOversampleDataGet()
997 ulAccum += HWREG(ulBase + ADC_SSFIFO); in ADCSoftwareOversampleDataGet()
1034 ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor) in ADCHardwareOversampleConfigure() argument
1041 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCHardwareOversampleConfigure()
1056 HWREG(ulBase + ADC_O_SAC) = ulValue; in ADCHardwareOversampleConfigure()
1131 ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp, in ADCComparatorConfigure() argument
1137 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCComparatorConfigure()
1143 HWREG(ulBase + ADC_O_DCCTL0 + (ulComp * 4)) = ulConfig; in ADCComparatorConfigure()
1167 ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp, in ADCComparatorRegionSet() argument
1173 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCComparatorRegionSet()
1181 HWREG(ulBase + ADC_O_DCCMP0 + (ulComp * 4)) = (ulHighRef << 16) | ulLowRef; in ADCComparatorRegionSet()
1201 ADCComparatorReset(unsigned long ulBase, unsigned long ulComp, in ADCComparatorReset() argument
1209 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCComparatorReset()
1225 HWREG(ulBase + ADC_O_DCRIC) = ulTemp; in ADCComparatorReset()
1241 ADCComparatorIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) in ADCComparatorIntDisable() argument
1246 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCComparatorIntDisable()
1252 HWREG(ulBase + ADC_O_IM) &= ~(0x10000 << ulSequenceNum); in ADCComparatorIntDisable()
1268 ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) in ADCComparatorIntEnable() argument
1273 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCComparatorIntEnable()
1279 HWREG(ulBase + ADC_O_IM) |= 0x10000 << ulSequenceNum; in ADCComparatorIntEnable()
1295 ADCComparatorIntStatus(unsigned long ulBase) in ADCComparatorIntStatus() argument
1300 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCComparatorIntStatus()
1305 return(HWREG(ulBase + ADC_O_DCISC)); in ADCComparatorIntStatus()
1321 ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus) in ADCComparatorIntClear() argument
1326 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCComparatorIntClear()
1331 HWREG(ulBase + ADC_O_DCISC) = ulStatus; in ADCComparatorIntClear()
1357 ADCReferenceSet(unsigned long ulBase, unsigned long ulRef) in ADCReferenceSet() argument
1362 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCReferenceSet()
1369 HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF_M) | in ADCReferenceSet()
1390 ADCReferenceGet(unsigned long ulBase) in ADCReferenceGet() argument
1395 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCReferenceGet()
1400 return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF_M); in ADCReferenceGet()
1421 ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution) in ADCResolutionSet() argument
1426 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCResolutionSet()
1432 HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_RES) | in ADCResolutionSet()
1454 ADCResolutionGet(unsigned long ulBase) in ADCResolutionGet() argument
1459 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCResolutionGet()
1464 return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_RES); in ADCResolutionGet()
1494 ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase) in ADCPhaseDelaySet() argument
1499 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCPhaseDelaySet()
1512 HWREG(ulBase + ADC_O_SPC) = ulPhase; in ADCPhaseDelaySet()
1532 ADCPhaseDelayGet(unsigned long ulBase) in ADCPhaseDelayGet() argument
1537 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCPhaseDelayGet()
1542 return(HWREG(ulBase + ADC_O_SPC)); in ADCPhaseDelayGet()