Lines Matching refs:HWREG
64 HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; in I2STxEnable()
69 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN; in I2STxEnable()
96 HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_TXEN; in I2STxDisable()
142 while(HWREG(ulBase + I2S_O_TXLEV) >= 16) in I2STxDataPut()
149 HWREG(ulBase + I2S_O_TXFIFO) = ulData; in I2STxDataPut()
195 if(HWREG(ulBase + I2S_O_TXLEV) < 16) in I2STxDataPutNonBlocking()
197 HWREG(ulBase + I2S_O_TXFIFO) = ulData; in I2STxDataPutNonBlocking()
262 HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS; in I2STxConfigSet()
271 HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; in I2STxConfigSet()
279 HWREG(ulBase + I2S_O_TXCFG) = ulConfig; in I2STxConfigSet()
320 HWREG(ulBase + I2S_O_TXLIMIT) = ulLevel; in I2STxFIFOLimitSet()
347 return(HWREG(ulBase + I2S_O_TXLIMIT)); in I2STxFIFOLimitGet()
381 return(HWREG(ulBase + I2S_O_TXLEV)); in I2STxFIFOLevelGet()
408 HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; in I2SRxEnable()
413 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN; in I2SRxEnable()
440 HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN; in I2SRxDisable()
485 while(HWREG(ulBase + I2S_O_RXLEV) == 0) in I2SRxDataGet()
492 *pulData = HWREG(ulBase + I2S_O_RXFIFO); in I2SRxDataGet()
537 if(HWREG(ulBase + I2S_O_RXLEV) != 0) in I2SRxDataGetNonBlocking()
539 *pulData = HWREG(ulBase + I2S_O_RXFIFO); in I2SRxDataGetNonBlocking()
592 HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; in I2SRxConfigSet()
599 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; in I2SRxConfigSet()
607 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; in I2SRxConfigSet()
622 HWREG(ulBase + I2S_O_RXCFG) = ulConfig; in I2SRxConfigSet()
664 HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel; in I2SRxFIFOLimitSet()
692 return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE); in I2SRxFIFOLimitGet()
726 return(HWREG(ulBase + I2S_O_RXLEV)); in I2SRxFIFOLevelGet()
754 HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; in I2STxRxEnable()
759 HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; in I2STxRxEnable()
764 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN; in I2STxRxEnable()
791 HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN); in I2STxRxDisable()
842 HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; in I2STxRxConfigSet()
843 HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; in I2STxRxConfigSet()
850 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; in I2STxRxConfigSet()
859 HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS; in I2STxRxConfigSet()
860 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; in I2STxRxConfigSet()
868 HWREG(ulBase + I2S_O_TXCFG) = ulConfig; in I2STxRxConfigSet()
869 HWREG(ulBase + I2S_O_RXCFG) = ulConfig; in I2STxRxConfigSet()
906 ulConfig = HWREG(ulBase + I2S_O_CFG) & in I2SMasterClockSelect()
908 HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock; in I2SMasterClockSelect()
943 HWREG(ulBase + I2S_O_IM) |= ulIntFlags; in I2SIntEnable()
974 HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags; in I2SIntDisable()
1007 return(HWREG(ulBase + I2S_O_MIS)); in I2SIntStatus()
1011 return(HWREG(ulBase + I2S_O_RIS)); in I2SIntStatus()
1053 HWREG(ulBase + I2S_O_IC) = ulIntFlags; in I2SIntClear()