Lines Matching refs:ulBase
54 I2STxEnable(unsigned long ulBase) in I2STxEnable() argument
59 ASSERT(ulBase == I2S0_BASE); in I2STxEnable()
64 HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; in I2STxEnable()
69 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN; in I2STxEnable()
86 I2STxDisable(unsigned long ulBase) in I2STxDisable() argument
91 ASSERT(ulBase == I2S0_BASE); in I2STxDisable()
96 HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_TXEN; in I2STxDisable()
132 I2STxDataPut(unsigned long ulBase, unsigned long ulData) in I2STxDataPut() argument
137 ASSERT(ulBase == I2S0_BASE); in I2STxDataPut()
142 while(HWREG(ulBase + I2S_O_TXLEV) >= 16) in I2STxDataPut()
149 HWREG(ulBase + I2S_O_TXFIFO) = ulData; in I2STxDataPut()
185 I2STxDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) in I2STxDataPutNonBlocking() argument
190 ASSERT(ulBase == I2S0_BASE); in I2STxDataPutNonBlocking()
195 if(HWREG(ulBase + I2S_O_TXLEV) < 16) in I2STxDataPutNonBlocking()
197 HWREG(ulBase + I2S_O_TXFIFO) = ulData; in I2STxDataPutNonBlocking()
240 I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) in I2STxConfigSet() argument
245 ASSERT(ulBase == I2S0_BASE); in I2STxConfigSet()
262 HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS; in I2STxConfigSet()
271 HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; in I2STxConfigSet()
279 HWREG(ulBase + I2S_O_TXCFG) = ulConfig; in I2STxConfigSet()
309 I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel) in I2STxFIFOLimitSet() argument
314 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitSet()
320 HWREG(ulBase + I2S_O_TXLIMIT) = ulLevel; in I2STxFIFOLimitSet()
337 I2STxFIFOLimitGet(unsigned long ulBase) in I2STxFIFOLimitGet() argument
342 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitGet()
347 return(HWREG(ulBase + I2S_O_TXLIMIT)); in I2STxFIFOLimitGet()
371 I2STxFIFOLevelGet(unsigned long ulBase) in I2STxFIFOLevelGet() argument
376 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLevelGet()
381 return(HWREG(ulBase + I2S_O_TXLEV)); in I2STxFIFOLevelGet()
398 I2SRxEnable(unsigned long ulBase) in I2SRxEnable() argument
403 ASSERT(ulBase == I2S0_BASE); in I2SRxEnable()
408 HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; in I2SRxEnable()
413 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN; in I2SRxEnable()
430 I2SRxDisable(unsigned long ulBase) in I2SRxDisable() argument
435 ASSERT(ulBase == I2S0_BASE); in I2SRxDisable()
440 HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN; in I2SRxDisable()
475 I2SRxDataGet(unsigned long ulBase, unsigned long *pulData) in I2SRxDataGet() argument
480 ASSERT(ulBase == I2S0_BASE); in I2SRxDataGet()
485 while(HWREG(ulBase + I2S_O_RXLEV) == 0) in I2SRxDataGet()
492 *pulData = HWREG(ulBase + I2S_O_RXFIFO); in I2SRxDataGet()
527 I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) in I2SRxDataGetNonBlocking() argument
532 ASSERT(ulBase == I2S0_BASE); in I2SRxDataGetNonBlocking()
537 if(HWREG(ulBase + I2S_O_RXLEV) != 0) in I2SRxDataGetNonBlocking()
539 *pulData = HWREG(ulBase + I2S_O_RXFIFO); in I2SRxDataGetNonBlocking()
579 I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) in I2SRxConfigSet() argument
584 ASSERT(ulBase == I2S0_BASE); in I2SRxConfigSet()
592 HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; in I2SRxConfigSet()
599 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; in I2SRxConfigSet()
607 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; in I2SRxConfigSet()
622 HWREG(ulBase + I2S_O_RXCFG) = ulConfig; in I2SRxConfigSet()
653 I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel) in I2SRxFIFOLimitSet() argument
658 ASSERT(ulBase == I2S0_BASE); in I2SRxFIFOLimitSet()
664 HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel; in I2SRxFIFOLimitSet()
681 I2SRxFIFOLimitGet(unsigned long ulBase) in I2SRxFIFOLimitGet() argument
686 ASSERT(ulBase == I2S0_BASE); in I2SRxFIFOLimitGet()
692 return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE); in I2SRxFIFOLimitGet()
716 I2SRxFIFOLevelGet(unsigned long ulBase) in I2SRxFIFOLevelGet() argument
721 ASSERT(ulBase == I2S0_BASE); in I2SRxFIFOLevelGet()
726 return(HWREG(ulBase + I2S_O_RXLEV)); in I2SRxFIFOLevelGet()
744 I2STxRxEnable(unsigned long ulBase) in I2STxRxEnable() argument
749 ASSERT(ulBase == I2S0_BASE); in I2STxRxEnable()
754 HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; in I2STxRxEnable()
759 HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; in I2STxRxEnable()
764 HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN; in I2STxRxEnable()
781 I2STxRxDisable(unsigned long ulBase) in I2STxRxDisable() argument
786 ASSERT(ulBase == I2S0_BASE); in I2STxRxDisable()
791 HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN); in I2STxRxDisable()
828 I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) in I2STxRxConfigSet() argument
833 ASSERT(ulBase == I2S0_BASE); in I2STxRxConfigSet()
842 HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; in I2STxRxConfigSet()
843 HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; in I2STxRxConfigSet()
850 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; in I2STxRxConfigSet()
859 HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS; in I2STxRxConfigSet()
860 HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; in I2STxRxConfigSet()
868 HWREG(ulBase + I2S_O_TXCFG) = ulConfig; in I2STxRxConfigSet()
869 HWREG(ulBase + I2S_O_RXCFG) = ulConfig; in I2STxRxConfigSet()
893 I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock) in I2SMasterClockSelect() argument
900 ASSERT(ulBase == I2S0_BASE); in I2SMasterClockSelect()
906 ulConfig = HWREG(ulBase + I2S_O_CFG) & in I2SMasterClockSelect()
908 HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock; in I2SMasterClockSelect()
931 I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags) in I2SIntEnable() argument
936 ASSERT(ulBase == I2S0_BASE); in I2SIntEnable()
943 HWREG(ulBase + I2S_O_IM) |= ulIntFlags; in I2SIntEnable()
962 I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags) in I2SIntDisable() argument
967 ASSERT(ulBase == I2S0_BASE); in I2SIntDisable()
974 HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags; in I2SIntDisable()
994 I2SIntStatus(unsigned long ulBase, tBoolean bMasked) in I2SIntStatus() argument
999 ASSERT(ulBase == I2S0_BASE); in I2SIntStatus()
1007 return(HWREG(ulBase + I2S_O_MIS)); in I2SIntStatus()
1011 return(HWREG(ulBase + I2S_O_RIS)); in I2SIntStatus()
1041 I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags) in I2SIntClear() argument
1046 ASSERT(ulBase == I2S0_BASE); in I2SIntClear()
1053 HWREG(ulBase + I2S_O_IC) = ulIntFlags; in I2SIntClear()
1076 I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) in I2SIntRegister() argument
1081 ASSERT(ulBase == I2S0_BASE); in I2SIntRegister()
1111 I2SIntUnregister(unsigned long ulBase) in I2SIntUnregister() argument
1116 ASSERT(ulBase == I2S0_BASE); in I2SIntUnregister()