Lines Matching refs:ulBase
84 UARTBaseValid(unsigned long ulBase) in UARTBaseValid() argument
86 return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || in UARTBaseValid()
87 (ulBase == UART2_BASE) || (ulBase == UART3_BASE) || in UARTBaseValid()
88 (ulBase == UART4_BASE) || (ulBase == UART5_BASE) || in UARTBaseValid()
89 (ulBase == UART6_BASE) || (ulBase == UART7_BASE)); in UARTBaseValid()
107 UARTIntNumberGet(unsigned long ulBase) in UARTIntNumberGet() argument
121 if(g_ppulUARTIntMap[ulIdx][0] == ulBase) in UARTIntNumberGet()
154 UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) in UARTParityModeSet() argument
159 ASSERT(UARTBaseValid(ulBase)); in UARTParityModeSet()
169 HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & in UARTParityModeSet()
189 UARTParityModeGet(unsigned long ulBase) in UARTParityModeGet() argument
194 ASSERT(UARTBaseValid(ulBase)); in UARTParityModeGet()
199 return(HWREG(ulBase + UART_O_LCRH) & in UARTParityModeGet()
222 UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, in UARTFIFOLevelSet() argument
228 ASSERT(UARTBaseValid(ulBase)); in UARTFIFOLevelSet()
243 HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; in UARTFIFOLevelSet()
265 UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, in UARTFIFOLevelGet() argument
273 ASSERT(UARTBaseValid(ulBase)); in UARTFIFOLevelGet()
278 ulTemp = HWREG(ulBase + UART_O_IFLS); in UARTFIFOLevelGet()
329 UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, in UARTConfigSetExpClk() argument
337 ASSERT(UARTBaseValid(ulBase)); in UARTConfigSetExpClk()
344 UARTDisable(ulBase); in UARTConfigSetExpClk()
355 HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; in UARTConfigSetExpClk()
368 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); in UARTConfigSetExpClk()
379 HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; in UARTConfigSetExpClk()
380 HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; in UARTConfigSetExpClk()
385 HWREG(ulBase + UART_O_LCRH) = ulConfig; in UARTConfigSetExpClk()
390 HWREG(ulBase + UART_O_FR) = 0; in UARTConfigSetExpClk()
395 UARTEnable(ulBase); in UARTConfigSetExpClk()
432 UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, in UARTConfigGetExpClk() argument
440 ASSERT(UARTBaseValid(ulBase)); in UARTConfigGetExpClk()
445 ulInt = HWREG(ulBase + UART_O_IBRD); in UARTConfigGetExpClk()
446 ulFrac = HWREG(ulBase + UART_O_FBRD); in UARTConfigGetExpClk()
452 if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) in UARTConfigGetExpClk()
464 *pulConfig = (HWREG(ulBase + UART_O_LCRH) & in UARTConfigGetExpClk()
482 UARTEnable(unsigned long ulBase) in UARTEnable() argument
487 ASSERT(UARTBaseValid(ulBase)); in UARTEnable()
492 HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; in UARTEnable()
497 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | in UARTEnable()
514 UARTDisable(unsigned long ulBase) in UARTDisable() argument
519 ASSERT(UARTBaseValid(ulBase)); in UARTDisable()
524 while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) in UARTDisable()
531 HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); in UARTDisable()
536 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | in UARTDisable()
552 UARTFIFOEnable(unsigned long ulBase) in UARTFIFOEnable() argument
557 ASSERT(UARTBaseValid(ulBase)); in UARTFIFOEnable()
562 HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; in UARTFIFOEnable()
577 UARTFIFODisable(unsigned long ulBase) in UARTFIFODisable() argument
582 ASSERT(UARTBaseValid(ulBase)); in UARTFIFODisable()
587 HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); in UARTFIFODisable()
614 UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower) in UARTEnableSIR() argument
619 ASSERT(UARTBaseValid(ulBase)); in UARTEnableSIR()
626 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP); in UARTEnableSIR()
630 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN); in UARTEnableSIR()
656 UARTDisableSIR(unsigned long ulBase) in UARTDisableSIR() argument
661 ASSERT(UARTBaseValid(ulBase)); in UARTDisableSIR()
666 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP); in UARTDisableSIR()
687 UARTSmartCardEnable(unsigned long ulBase) in UARTSmartCardEnable() argument
695 ASSERT(UARTBaseValid(ulBase)); in UARTSmartCardEnable()
702 ulVal = HWREG(ulBase + UART_O_LCRH); in UARTSmartCardEnable()
706 HWREG(ulBase + UART_O_LCRH) = ulVal; in UARTSmartCardEnable()
711 HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART; in UARTSmartCardEnable()
731 UARTSmartCardDisable(unsigned long ulBase) in UARTSmartCardDisable() argument
737 ASSERT(UARTBaseValid(ulBase)); in UARTSmartCardDisable()
742 HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART; in UARTSmartCardDisable()
769 UARTModemControlSet(unsigned long ulBase, unsigned long ulControl) in UARTModemControlSet() argument
777 ASSERT(ulBase == UART1_BASE); in UARTModemControlSet()
783 ulTemp = HWREG(ulBase + UART_O_CTL); in UARTModemControlSet()
785 HWREG(ulBase + UART_O_CTL) = ulTemp; in UARTModemControlSet()
812 UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) in UARTModemControlClear() argument
820 ASSERT(ulBase == UART1_BASE); in UARTModemControlClear()
826 ulTemp = HWREG(ulBase + UART_O_CTL); in UARTModemControlClear()
828 HWREG(ulBase + UART_O_CTL) = ulTemp; in UARTModemControlClear()
851 UARTModemControlGet(unsigned long ulBase) in UARTModemControlGet() argument
857 ASSERT(ulBase == UART1_BASE); in UARTModemControlGet()
859 return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); in UARTModemControlGet()
882 UARTModemStatusGet(unsigned long ulBase) in UARTModemStatusGet() argument
888 ASSERT(ulBase == UART1_BASE); in UARTModemStatusGet()
890 return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | in UARTModemStatusGet()
920 UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) in UARTFlowControlSet() argument
926 ASSERT(UARTBaseValid(ulBase)); in UARTFlowControlSet()
932 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTFlowControlSet()
957 UARTFlowControlGet(unsigned long ulBase) in UARTFlowControlGet() argument
963 ASSERT(UARTBaseValid(ulBase)); in UARTFlowControlGet()
965 return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | in UARTFlowControlGet()
995 UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) in UARTTxIntModeSet() argument
1000 ASSERT(UARTBaseValid(ulBase)); in UARTTxIntModeSet()
1007 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTTxIntModeSet()
1034 UARTTxIntModeGet(unsigned long ulBase) in UARTTxIntModeGet() argument
1039 ASSERT(UARTBaseValid(ulBase)); in UARTTxIntModeGet()
1044 return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | in UARTTxIntModeGet()
1062 UARTCharsAvail(unsigned long ulBase) in UARTCharsAvail() argument
1067 ASSERT(UARTBaseValid(ulBase)); in UARTCharsAvail()
1072 return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); in UARTCharsAvail()
1089 UARTSpaceAvail(unsigned long ulBase) in UARTSpaceAvail() argument
1094 ASSERT(UARTBaseValid(ulBase)); in UARTSpaceAvail()
1099 return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); in UARTSpaceAvail()
1122 UARTCharGetNonBlocking(unsigned long ulBase) in UARTCharGetNonBlocking() argument
1127 ASSERT(UARTBaseValid(ulBase)); in UARTCharGetNonBlocking()
1132 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) in UARTCharGetNonBlocking()
1137 return(HWREG(ulBase + UART_O_DR)); in UARTCharGetNonBlocking()
1163 UARTCharGet(unsigned long ulBase) in UARTCharGet() argument
1168 ASSERT(UARTBaseValid(ulBase)); in UARTCharGet()
1173 while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) in UARTCharGet()
1180 return(HWREG(ulBase + UART_O_DR)); in UARTCharGet()
1205 UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) in UARTCharPutNonBlocking() argument
1210 ASSERT(UARTBaseValid(ulBase)); in UARTCharPutNonBlocking()
1215 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) in UARTCharPutNonBlocking()
1220 HWREG(ulBase + UART_O_DR) = ucData; in UARTCharPutNonBlocking()
1251 UARTCharPut(unsigned long ulBase, unsigned char ucData) in UARTCharPut() argument
1256 ASSERT(UARTBaseValid(ulBase)); in UARTCharPut()
1261 while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) in UARTCharPut()
1268 HWREG(ulBase + UART_O_DR) = ucData; in UARTCharPut()
1287 UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) in UARTBreakCtl() argument
1292 ASSERT(UARTBaseValid(ulBase)); in UARTBreakCtl()
1297 HWREG(ulBase + UART_O_LCRH) = in UARTBreakCtl()
1299 (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : in UARTBreakCtl()
1300 (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); in UARTBreakCtl()
1319 UARTBusy(unsigned long ulBase) in UARTBusy() argument
1324 ASSERT(UARTBaseValid(ulBase)); in UARTBusy()
1329 return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); in UARTBusy()
1352 UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) in UARTIntRegister() argument
1359 ASSERT(UARTBaseValid(ulBase)); in UARTIntRegister()
1364 ulInt = UARTIntNumberGet(ulBase); in UARTIntRegister()
1395 UARTIntUnregister(unsigned long ulBase) in UARTIntUnregister() argument
1402 ASSERT(UARTBaseValid(ulBase)); in UARTIntUnregister()
1407 ulInt = UARTIntNumberGet(ulBase); in UARTIntUnregister()
1450 UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) in UARTIntEnable() argument
1455 ASSERT(UARTBaseValid(ulBase)); in UARTIntEnable()
1460 HWREG(ulBase + UART_O_IM) |= ulIntFlags; in UARTIntEnable()
1481 UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) in UARTIntDisable() argument
1486 ASSERT(UARTBaseValid(ulBase)); in UARTIntDisable()
1491 HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); in UARTIntDisable()
1511 UARTIntStatus(unsigned long ulBase, tBoolean bMasked) in UARTIntStatus() argument
1516 ASSERT(UARTBaseValid(ulBase)); in UARTIntStatus()
1524 return(HWREG(ulBase + UART_O_MIS)); in UARTIntStatus()
1528 return(HWREG(ulBase + UART_O_RIS)); in UARTIntStatus()
1559 UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) in UARTIntClear() argument
1564 ASSERT(UARTBaseValid(ulBase)); in UARTIntClear()
1569 HWREG(ulBase + UART_O_ICR) = ulIntFlags; in UARTIntClear()
1595 UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) in UARTDMAEnable() argument
1600 ASSERT(UARTBaseValid(ulBase)); in UARTDMAEnable()
1605 HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; in UARTDMAEnable()
1627 UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) in UARTDMADisable() argument
1632 ASSERT(UARTBaseValid(ulBase)); in UARTDMADisable()
1637 HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; in UARTDMADisable()
1658 UARTRxErrorGet(unsigned long ulBase) in UARTRxErrorGet() argument
1663 ASSERT(UARTBaseValid(ulBase)); in UARTRxErrorGet()
1668 return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); in UARTRxErrorGet()
1686 UARTRxErrorClear(unsigned long ulBase) in UARTRxErrorClear() argument
1691 ASSERT(UARTBaseValid(ulBase)); in UARTRxErrorClear()
1697 HWREG(ulBase + UART_O_ECR) = 0; in UARTRxErrorClear()
1723 UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource) in UARTClockSourceSet() argument
1728 ASSERT(UARTBaseValid(ulBase)); in UARTClockSourceSet()
1734 HWREG(ulBase + UART_O_CC) = ulSource; in UARTClockSourceSet()
1755 UARTClockSourceGet(unsigned long ulBase) in UARTClockSourceGet() argument
1760 ASSERT(UARTBaseValid(ulBase)); in UARTClockSourceGet()
1765 return(HWREG(ulBase + UART_O_CC)); in UARTClockSourceGet()
1784 UART9BitEnable(unsigned long ulBase) in UART9BitEnable() argument
1789 ASSERT(UARTBaseValid(ulBase)); in UART9BitEnable()
1794 HWREG(ulBase + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN; in UART9BitEnable()
1813 UART9BitDisable(unsigned long ulBase) in UART9BitDisable() argument
1818 ASSERT(UARTBaseValid(ulBase)); in UART9BitDisable()
1823 HWREG(ulBase + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN; in UART9BitDisable()
1848 UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr, in UART9BitAddrSet() argument
1854 ASSERT(UARTBaseValid(ulBase)); in UART9BitAddrSet()
1859 HWREG(ulBase + UART_O_9BITADDR) = ucAddr << UART_9BITADDR_ADDR_S; in UART9BitAddrSet()
1860 HWREG(ulBase + UART_O_9BITAMASK) = ucMask << UART_9BITAMASK_MASK_S; in UART9BitAddrSet()
1887 UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr) in UART9BitAddrSend() argument
1894 ASSERT(UARTBaseValid(ulBase)); in UART9BitAddrSend()
1899 while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) in UART9BitAddrSend()
1906 ulLCRH = HWREG(ulBase + UART_O_LCRH); in UART9BitAddrSend()
1907 HWREG(ulBase + UART_O_LCRH) = ((ulLCRH & ~UART_LCRH_EPS) | UART_LCRH_SPS | in UART9BitAddrSend()
1913 HWREG(ulBase + UART_O_DR) = ucAddr; in UART9BitAddrSend()
1918 while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) in UART9BitAddrSend()
1925 HWREG(ulBase + UART_O_LCRH) = ulLCRH; in UART9BitAddrSend()