Lines Matching refs:LIOINTC0_BASE
37 HWREG8(LIOINTC0_BASE + i) = LIOINTC_COREx_INTy(0, 0); in liointc_init()
47 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_DISABLE) = 0xffffffff; in liointc_init()
51 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) = 0x0; in liointc_init()
52 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) = 0x0; in liointc_init()
65 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq)); in liointc_set_irq_mode()
66 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); in liointc_set_irq_mode()
70 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); in liointc_set_irq_mode()
71 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); in liointc_set_irq_mode()
75 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); in liointc_set_irq_mode()
76 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq)); in liointc_set_irq_mode()
80 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq)); in liointc_set_irq_mode()
81 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq)); in liointc_set_irq_mode()
85 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); in liointc_set_irq_mode()
86 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); in liointc_set_irq_mode()
206 liointc_isr(LIOINTC0_BASE, CORE0_INTISR0, LIOINTC0_IRQBASE); in rt_do_mips_cpu_irq()
218 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << irq); in rt_hw_interrupt_umask()
230 HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << irq); in rt_hw_interrupt_mask()