Lines Matching refs:LIOINTC1_BASE
43 HWREG8(LIOINTC1_BASE + i) = LIOINTC_COREx_INTy(0, 1); in liointc_init()
48 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_DISABLE) = 0xffffffff; in liointc_init()
54 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) = 0x0; in liointc_init()
55 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) = 0x0; in liointc_init()
93 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq - 32)); in liointc_set_irq_mode()
94 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); in liointc_set_irq_mode()
98 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); in liointc_set_irq_mode()
99 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); in liointc_set_irq_mode()
103 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); in liointc_set_irq_mode()
104 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32)); in liointc_set_irq_mode()
108 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq - 32)); in liointc_set_irq_mode()
109 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32)); in liointc_set_irq_mode()
113 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); in liointc_set_irq_mode()
114 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); in liointc_set_irq_mode()
210 liointc_isr(LIOINTC1_BASE, CORE0_INTISR1, LIOINTC1_IRQBASE); in rt_do_mips_cpu_irq()
222 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << (irq - 32)); in rt_hw_interrupt_umask()
234 HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << (irq - 32)); in rt_hw_interrupt_mask()