Lines Matching refs:Vector
10 ; Fixed Vector Table
28 ; Variable Vector Table
38 .long _os_context_switch ; Vector 0: BRK
39 .long 0 ; Vector 1: Reserved
40 .long 0 ; Vector 2: Reserved
41 .long 0 ; Vector 3: Reserved
42 .long 0 ; Vector 4: INT3
43 .long 0 ; Vector 5: Timer B5
44 .long 0 ; Vector 6: Timer B4, UART1 Bus Collision Detect
45 .long 0 ; Vector 7: Timer B3, UART0 Bus Collision Detect
46 .long 0 ; Vector 8: SI/O4, INT5
47 .long 0 ; Vector 9: SI/O3, INT4
48 .long 0 ; Vector 10: UART2 Bus Collision Detect
49 .long 0 ; Vector 11: DMA0
50 .long 0 ; Vector 12: DMA1
51 .long 0 ; Vector 13: Key Input Interrupt
52 .long 0 ; Vector 14: A/D
53 .long 0 ; Vector 15: UART2 Transmit, NACK2
54 .long 0 ; Vector 16: UART2 Receive, ACK2
55 .long 0 ; Vector 17: UART0 Transmit, NACK0
56 .long _rt_hw_uart0_receive_handler ; Vector 18: UART0 Receive, ACK0
57 .long 0 ; Vector 19: UART1 Transmit, NACK1
58 .long 0 ; Vector 20: UART1 Receive, ACK1
59 .long 0 ; Vector 21: Timer A0
60 .long 0 ; Vector 22: Timer A1
61 .long 0 ; Vector 23: Timer A2
62 .long 0 ; Vector 24: Timer A3
63 .long 0 ; Vector 25: Timer A4
64 .long _rt_hw_timer_handler ; Vector 26: Timer B0
65 .long 0 ; Vector 27: Timer B1
66 .long 0 ; Vector 28: Timer B2
67 .long 0 ; Vector 29:
68 .long 0 ; Vector 30:
69 .long 0 ; Vector 31: