Lines Matching refs:Vector
30 DC32 os_context_switch ; Vector 0: BRK
31 DC32 0 ; Vector 1: Reserved
32 DC32 0 ; Vector 2: Reserved
33 DC32 0 ; Vector 3: Reserved
34 DC32 0 ; Vector 4: INT3
35 DC32 0 ; Vector 5: Timer B5
36 DC32 0 ; Vector 6: Timer B4, UART1 Bus Collision Detect
37 DC32 0 ; Vector 7: Timer B3, UART0 Bus Collision Detect
38 DC32 0 ; Vector 8: SI/O4, INT5
39 DC32 0 ; Vector 9: SI/O3, INT4
40 DC32 0 ; Vector 10: UART2 Bus Collision Detect
41 DC32 0 ; Vector 11: DMA0
42 DC32 0 ; Vector 12: DMA1
43 DC32 0 ; Vector 13: Key Input Interrupt
44 DC32 0 ; Vector 14: A/D
45 DC32 0 ; Vector 15: UART2 Transmit, NACK2
46 DC32 0 ; Vector 16: UART2 Receive, ACK2
47 DC32 0 ; Vector 17: UART0 Transmit, NACK0
48 DC32 rt_hw_uart0_receive_handler ; Vector 18: UART0 Receive, ACK0
49 DC32 0 ; Vector 19: UART1 Transmit, NACK1
50 DC32 0 ; Vector 20: UART1 Receive, ACK1
51 DC32 0 ; Vector 21: Timer A0
52 DC32 0 ; Vector 22: Timer A1
53 DC32 0 ; Vector 23: Timer A2
54 DC32 0 ; Vector 24: Timer A3
55 DC32 0 ; Vector 25: Timer A4
56 DC32 rt_hw_timer_handler ; Vector 26: Timer B0
57 DC32 0 ; Vector 27: Timer B1
58 DC32 0 ; Vector 28: Timer B2
59 DC32 0 ; Vector 29:
60 DC32 0 ; Vector 30:
61 DC32 0 ; Vector 31: