Lines Matching refs:CFGR
174 RCC->CFGR &= (u32)0xF8FFC00C; in SystemInit()
183 RCC->CFGR &= (u32)0xFF3CFFFF; in SystemInit()
313 RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; in SetSysClockToHSE()
316 RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; in SetSysClockToHSE()
319 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; in SetSysClockToHSE()
322 RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); in SetSysClockToHSE()
323 RCC->CFGR |= (u32)RCC_CFGR_SW_HSE; in SetSysClockToHSE()
326 while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x04) { in SetSysClockToHSE()
373 RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; in SetSysClockTo24()
376 RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; in SetSysClockTo24()
379 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; in SetSysClockTo24()
396 RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); in SetSysClockTo24()
397 RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; in SetSysClockTo24()
400 while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { in SetSysClockTo24()
448 RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; in SetSysClockTo36()
451 RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; in SetSysClockTo36()
454 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; in SetSysClockTo36()
469 RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); in SetSysClockTo36()
470 RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; in SetSysClockTo36()
473 while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { in SetSysClockTo36()
519 RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; in SetSysClockTo48()
522 RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; in SetSysClockTo48()
525 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; in SetSysClockTo48()
542 RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); in SetSysClockTo48()
543 RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; in SetSysClockTo48()
546 while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { in SetSysClockTo48()
609 RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2); in SetSysClockToXX()
612 RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4; in SetSysClockToXX()
615 RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; in SetSysClockToXX()
619 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4; in SetSysClockToXX()
623 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; in SetSysClockToXX()
644 RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); in SetSysClockToXX()
645 RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; in SetSysClockToXX()
648 while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) { in SetSysClockToXX()
654 RCC->CFGR &= (~(RCC_CFGR_PPRE_0)); in SetSysClockToXX()
658 RCC->CFGR &= (~(RCC_CFGR_PPRE_3)); in SetSysClockToXX()
673 RCC->CFGR = RCC_CFGR_PPRE1_2; in SetSysClockTo24_HSI()
687 RCC->CFGR &= ~RCC_CFGR_SW; in SetSysClockTo24_HSI()
689 RCC->CFGR |= RCC_CFGR_SW_PLL; in SetSysClockTo24_HSI()
692 temp = RCC->CFGR >> 2; in SetSysClockTo24_HSI()
706 RCC->CFGR = RCC_CFGR_PPRE1_2; in SetSysClockTo36_HSI()
719 RCC->CFGR &= ~ RCC_CFGR_SW; in SetSysClockTo36_HSI()
721 RCC->CFGR |= RCC_CFGR_SW_PLL; in SetSysClockTo36_HSI()
724 temp = RCC->CFGR >> 2; in SetSysClockTo36_HSI()
738 RCC->CFGR = RCC_CFGR_PPRE1_2; in SetSysClockTo48_HSI()
756 RCC->CFGR &= ~RCC_CFGR_SW; in SetSysClockTo48_HSI()
758 RCC->CFGR |= RCC_CFGR_SW_PLL; in SetSysClockTo48_HSI()
761 temp = RCC->CFGR >> 2; in SetSysClockTo48_HSI()
795 RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2); in SetSysClockToXX_HSI()
797 RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4; in SetSysClockToXX_HSI()
800 RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; in SetSysClockToXX_HSI()
804 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4; in SetSysClockToXX_HSI()
808 RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; in SetSysClockToXX_HSI()
831 RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); in SetSysClockToXX_HSI()
832 RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; in SetSysClockToXX_HSI()
835 while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) { in SetSysClockToXX_HSI()
841 RCC->CFGR &= (~(RCC_CFGR_PPRE_0)); in SetSysClockToXX_HSI()
845 RCC->CFGR &= (~(RCC_CFGR_PPRE_3)); in SetSysClockToXX_HSI()