Lines Matching refs:_IOMUXC_SetPinConfig
135 static inline void _IOMUXC_SetPinConfig(uint32_t muxRegister, in _IOMUXC_SetPinConfig() function
155 _IOMUXC_SetPinConfig(IOMUXC_UART1_RTS_B_USDHC1_CD_B, in _mmcsd_gpio_init()
161 _IOMUXC_SetPinConfig(IOMUXC_SD1_CLK_USDHC1_CLK, in _mmcsd_gpio_init()
171 _IOMUXC_SetPinConfig(IOMUXC_SD1_CMD_USDHC1_CMD, in _mmcsd_gpio_init()
181 _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA0_USDHC1_DATA0, in _mmcsd_gpio_init()
191 _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA1_USDHC1_DATA1, in _mmcsd_gpio_init()
201 _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA2_USDHC1_DATA2, in _mmcsd_gpio_init()
211 _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA3_USDHC1_DATA3, in _mmcsd_gpio_init()
226 _IOMUXC_SetPinConfig(IOMUXC_NAND_WE_B_USDHC2_CMD, in _mmcsd_gpio_init()
236 _IOMUXC_SetPinConfig(IOMUXC_NAND_RE_B_USDHC2_CLK, in _mmcsd_gpio_init()
245 _IOMUXC_SetPinConfig(IOMUXC_NAND_ALE_USDHC2_RESET_B, in _mmcsd_gpio_init()
254 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA00_USDHC2_DATA0, in _mmcsd_gpio_init()
263 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA01_USDHC2_DATA1, in _mmcsd_gpio_init()
272 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA02_USDHC2_DATA2, in _mmcsd_gpio_init()
281 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA03_USDHC2_DATA3, in _mmcsd_gpio_init()
290 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA04_USDHC2_DATA4, in _mmcsd_gpio_init()
299 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA05_USDHC2_DATA5, in _mmcsd_gpio_init()
308 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA06_USDHC2_DATA6, in _mmcsd_gpio_init()
317 _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA07_USDHC2_DATA7, in _mmcsd_gpio_init()