Lines Matching defs:BASE
59 #define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) argument
60 #define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) argument
61 #define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) argument
62 #define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) argument
63 #define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) argument
64 #define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) argument
65 #define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) argument
66 #define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) argument
67 #define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) argument
68 #define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) argument
69 #define PL011_REG_IFLS(BASE) HWREG32(BASE + 0x34) argument
70 #define PL011_REG_IMSC(BASE) HWREG32(BASE + 0x38) argument
71 #define PL011_REG_RIS(BASE) HWREG32(BASE + 0x3C) argument
72 #define PL011_REG_MIS(BASE) HWREG32(BASE + 0x40) argument
73 #define PL011_REG_ICR(BASE) HWREG32(BASE + 0x44) argument
74 #define PL011_REG_DMACR(BASE) HWREG32(BASE + 0x48) argument
75 #define PL011_REG_RESERVED2(BASE) HWREG32(BASE + 0x4C) argument
76 #define PL011_REG_ITCR(BASE) HWREG32(BASE + 0x80) argument
77 #define PL011_REG_ITIP(BASE) HWREG32(BASE + 0x84) argument
78 #define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88) argument
79 #define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C) argument
84 #define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ argument
85 #define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ argument
86 #define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ argument
87 #define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */ argument
88 #define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */ argument
89 #define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ argument
90 #define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ argument
91 #define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ argument
92 #define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ argument
93 #define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ argument
94 #define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */ argument
95 #define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */ argument
96 #define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ argument
97 #define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */ argument
98 #define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */ argument
99 #define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ argument
100 #define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ argument
101 #define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */ argument
102 #define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */ argument
103 #define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */ argument