Lines Matching refs:uint32
40 uint32 GCR0; /**< 0x0000 Global Control Register 0 */
41 uint32 GCR1; /**< 0x0004 Global Control Register 1 */
42 uint32 GCR2; /**< 0x0008 Global Control Register 2 */
43 uint32 SETINT; /**< 0x000C Set Interrupt Enable Register */
44 uint32 CLRINT; /**< 0x0010 Clear Interrupt Enable Register */
45 uint32 SETINTLVL; /**< 0x0014 Set Interrupt Level Register */
46 uint32 CLRINTLVL; /**< 0x0018 Set Interrupt Level Register */
47 uint32 FLR; /**< 0x001C Interrupt Flag Register */
48 uint32 INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */
49 uint32 INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */
50 uint32 FORMAT; /**< 0x0028 Format Control Register */
51 uint32 BRS; /**< 0x002C Baud Rate Selection Register */
52 uint32 ED; /**< 0x0030 Emulation Register */
53 uint32 RD; /**< 0x0034 Receive Data Buffer */
54 uint32 TD; /**< 0x0038 Transmit Data Buffer */
55 uint32 FUN; /**< 0x003C Pin Function Register */
56 uint32 DIR; /**< 0x0040 Pin Direction Register */
57 uint32 DIN; /**< 0x0044 Pin Data In Register */
58 uint32 DOUT; /**< 0x0048 Pin Data Out Register */
59 uint32 SET; /**< 0x004C Pin Data Set Register */
60 uint32 CLR; /**< 0x0050 Pin Data Clr Register */
61 uint32 ODR; /**< 0x0054: Pin Open Drain Output Enable Register */
62 uint32 PD; /**< 0x0058: Pin Pullup/Pulldown Disable Register */
63 uint32 PSL; /**< 0x005C: Pin Pullup/Pulldown Selection Register */
64 uint32 rsdv1[12U]; /**< 0x060: Reserved */
65 uint32 IODFTCTRL; /**< 0x0090: I/O Error Enable Register */