Lines Matching refs:uint32
161 uint32 SADD; /* initial source address */
162 uint32 DADD; /* initial destination address */
163 uint32 CHCTRL; /* channel count */
164 uint32 FRCNT; /* frame count */
165 uint32 ELCNT; /* element count */
166 uint32 ELDOFFSET; /* element destination offset */
167 uint32 ELSOFFSET; /* element source offset */
168 uint32 FRDOFFSET; /* frame detination offset */
169 uint32 FRSOFFSET; /* frame source offset */
170 uint32 PORTASGN; /* dma port */
171 uint32 RDSIZE; /* read element size */
172 uint32 WRSIZE; /* write element size */
173 uint32 TTYPE; /* trigger type - frame/block */
174 uint32 ADDMODERD; /* addresssing mode for source */
175 uint32 ADDMODEWR; /* addresssing mode for destination */
176 uint32 AUTOINIT; /* auto-init mode */
177 uint32 COMBO; /* next ctrl packet trigger */
185 uint32 ISADDR;
186 uint32 IDADDR;
187 uint32 ITCOUNT;
188 uint32 rsvd1;
189 uint32 CHCTRL;
190 uint32 EIOFF;
191 uint32 FIOFF;
192 uint32 rsvd2;
197 uint32 res[256U];
202 uint32 CSADDR;
203 uint32 CDADDR;
204 uint32 CTCOUNT;
205 uint32 rsvd3;
234 void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT);
235 void dmaSetChEnable(uint32 channel,uint32 type);
236 void dmaReqAssign(uint32 channel,uint32 reqline);
237 uint32 dmaGetReq(uint32 channel);
238 void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority);
239 void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype);
240 void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype);
241 void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add);