Lines Matching refs:uint32
71 #define LPO_TRIM_VALUE (((*(volatile uint32 *)0xF00801B4U) & 0xFFFF0000U)>>16U)
72 #define SYS_EXCEPTION (*(volatile uint32 *)0xFFFFFFE4U)
81 #define WATCHDOG_STATUS (*(volatile uint32 *)0xFFFFFC98U)
82 #define DEVICE_ID_REV (*(volatile uint32 *)0xFFFFFFF0U)
211 uint32 CONFIG_SYSPC1;
212 uint32 CONFIG_SYSPC2;
213 uint32 CONFIG_SYSPC7;
214 uint32 CONFIG_SYSPC8;
215 uint32 CONFIG_SYSPC9;
216 uint32 CONFIG_CSDIS;
217 uint32 CONFIG_CDDIS;
218 uint32 CONFIG_GHVSRC;
219 uint32 CONFIG_VCLKASRC;
220 uint32 CONFIG_RCLKSRC;
221 uint32 CONFIG_MSTGCR;
222 uint32 CONFIG_MINITGCR;
223 uint32 CONFIG_MSINENA;
224 uint32 CONFIG_PLLCTL1;
225 uint32 CONFIG_PLLCTL2;
226 uint32 CONFIG_UERFLAG;
227 uint32 CONFIG_LPOMONCTL;
228 uint32 CONFIG_CLKTEST;
229 uint32 CONFIG_DFTCTRLREG1;
230 uint32 CONFIG_DFTCTRLREG2;
231 uint32 CONFIG_GPREG1;
232 uint32 CONFIG_RAMGCR;
233 uint32 CONFIG_BMMCR1;
234 uint32 CONFIG_MMUGCR;
235 uint32 CONFIG_CLKCNTL;
236 uint32 CONFIG_ECPCNTL;
237 uint32 CONFIG_DEVCR1;
238 uint32 CONFIG_SYSECR;
239 uint32 CONFIG_PLLCTL3;
240 uint32 CONFIG_STCCLKDIV;
241 uint32 CONFIG_CLK2CNTL;
242 uint32 CONFIG_VCLKACON1;
243 uint32 CONFIG_CLKSLIP;
244 uint32 CONFIG_EFC_CTLEN;
381 #define FSM_WR_ENA_HL (*(volatile uint32 *)0xFFF87288U)
382 #define EEPROM_CONFIG_HL (*(volatile uint32 *)0xFFF872B8U)
387 uint32 CONFIG_FRDCNTL;
388 uint32 CONFIG_FEDACCTRL1;
389 uint32 CONFIG_FEDACCTRL2;
390 uint32 CONFIG_FEDACSDIS;
391 uint32 CONFIG_FBPROT;
392 uint32 CONFIG_FBSE;
393 uint32 CONFIG_FBAC;
394 uint32 CONFIG_FBFALLBACK;
395 uint32 CONFIG_FPAC1;
396 uint32 CONFIG_FPAC2;
397 uint32 CONFIG_FMAC;
398 uint32 CONFIG_FLOCK;
399 uint32 CONFIG_FDIAGCTRL;
400 uint32 CONFIG_FEDACSDIS2;
441 void systemPowerDown(uint32 mode);
450 uint32 CONFIG_RAMCTRL[2U];
451 uint32 CONFIG_RAMTHRESHOLD[2U];
452 uint32 CONFIG_RAMINTCTRL[2U];
453 uint32 CONFIG_RAMTEST[2U];
454 uint32 CONFIG_RAMADDRDECVECT[2U];