Lines Matching refs:module
60 static void _uart_write(struct uart_module *const module) in _uart_write() argument
63 Uart *const uart_hw = module->hw; in _uart_write()
66 uint8_t data_to_send = *(module->tx_buffer_ptr); in _uart_write()
68 (module->tx_buffer_ptr)++; in _uart_write()
74 (module->remaining_tx_buffer_length)--; in _uart_write()
84 struct uart_module *const module) in _uart_read() argument
87 Uart *const uart_hw = module->hw; in _uart_read()
92 *(module->rx_buffer_ptr) = received_data; in _uart_read()
94 module->rx_buffer_ptr += 1; in _uart_read()
97 module->remaining_rx_buffer_length--; in _uart_read()
102 struct uart_module *module = _uart_instances[0]; in uart_rx0_isr_handler() local
104 uint32_t flags = module->hw->RECEIVE_STATUS.reg; in uart_rx0_isr_handler()
107 module->status = STATUS_ERR_OVERFLOW; in uart_rx0_isr_handler()
109 module->hw->RX_INTERRUPT_MASK.reg &= in uart_rx0_isr_handler()
112 if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) && in uart_rx0_isr_handler()
113 (module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) { in uart_rx0_isr_handler()
114 (module->callback[UART_RX_FIFO_OVERRUN])(module); in uart_rx0_isr_handler()
117 uint8_t flush = module->hw->RECEIVE_DATA.reg; in uart_rx0_isr_handler()
121 _uart_read(module); in uart_rx0_isr_handler()
122 if (module->remaining_rx_buffer_length == 0) { in uart_rx0_isr_handler()
123 if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) && in uart_rx0_isr_handler()
124 (module->callback_reg_mask & (1 << UART_RX_COMPLETE))) { in uart_rx0_isr_handler()
125 module->status = STATUS_OK; in uart_rx0_isr_handler()
126 module->hw->RX_INTERRUPT_MASK.reg &= in uart_rx0_isr_handler()
128 (module->callback[UART_RX_COMPLETE])(module); in uart_rx0_isr_handler()
136 struct uart_module *module = _uart_instances[0]; in uart_tx0_isr_handler() local
138 uint32_t flags = module->hw->TRANSMIT_STATUS.reg; in uart_tx0_isr_handler()
140 _uart_write(module); in uart_tx0_isr_handler()
141 if (module->remaining_tx_buffer_length == 0) { in uart_tx0_isr_handler()
142 module->hw->TX_INTERRUPT_MASK.reg &= in uart_tx0_isr_handler()
144 module->hw->TX_INTERRUPT_MASK.reg |= in uart_tx0_isr_handler()
149 if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) && in uart_tx0_isr_handler()
150 (module->callback_reg_mask & (1 << UART_TX_COMPLETE))) { in uart_tx0_isr_handler()
151 module->status = STATUS_OK; in uart_tx0_isr_handler()
153 module->hw->TX_INTERRUPT_MASK.reg &= in uart_tx0_isr_handler()
155 (module->callback[UART_TX_COMPLETE])(module); in uart_tx0_isr_handler()
160 if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) && in uart_tx0_isr_handler()
161 (module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) { in uart_tx0_isr_handler()
162 (module->callback[UART_CTS_ACTIVE])(module); in uart_tx0_isr_handler()
170 struct uart_module *module = _uart_instances[1]; in uart_rx1_isr_handler() local
172 uint32_t flags = module->hw->RECEIVE_STATUS.reg; in uart_rx1_isr_handler()
175 module->status = STATUS_ERR_OVERFLOW; in uart_rx1_isr_handler()
177 module->hw->RX_INTERRUPT_MASK.reg &= in uart_rx1_isr_handler()
180 if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) && in uart_rx1_isr_handler()
181 (module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) { in uart_rx1_isr_handler()
182 (module->callback[UART_RX_FIFO_OVERRUN])(module); in uart_rx1_isr_handler()
185 uint8_t flush = module->hw->RECEIVE_DATA.reg; in uart_rx1_isr_handler()
189 _uart_read(module); in uart_rx1_isr_handler()
190 if (module->remaining_rx_buffer_length == 0) { in uart_rx1_isr_handler()
191 if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) && in uart_rx1_isr_handler()
192 (module->callback_reg_mask & (1 << UART_RX_COMPLETE))) { in uart_rx1_isr_handler()
193 module->status = STATUS_OK; in uart_rx1_isr_handler()
194 module->hw->RX_INTERRUPT_MASK.reg &= in uart_rx1_isr_handler()
196 (module->callback[UART_RX_COMPLETE])(module); in uart_rx1_isr_handler()
204 struct uart_module *module = _uart_instances[1]; in uart_tx1_isr_handler() local
206 uint32_t flags = module->hw->TRANSMIT_STATUS.reg; in uart_tx1_isr_handler()
208 _uart_write(module); in uart_tx1_isr_handler()
209 if (module->remaining_tx_buffer_length == 0) { in uart_tx1_isr_handler()
210 module->hw->TX_INTERRUPT_MASK.reg &= in uart_tx1_isr_handler()
212 module->hw->TX_INTERRUPT_MASK.reg |= in uart_tx1_isr_handler()
217 if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) && in uart_tx1_isr_handler()
218 (module->callback_reg_mask & (1 << UART_TX_COMPLETE))) { in uart_tx1_isr_handler()
219 module->status = STATUS_OK; in uart_tx1_isr_handler()
221 module->hw->TX_INTERRUPT_MASK.reg &= in uart_tx1_isr_handler()
223 (module->callback[UART_TX_COMPLETE])(module); in uart_tx1_isr_handler()
228 if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) && in uart_tx1_isr_handler()
229 (module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) { in uart_tx1_isr_handler()
230 (module->callback[UART_CTS_ACTIVE])(module); in uart_tx1_isr_handler()
236 static void uart_set_baudrate(struct uart_module *const module, in uart_set_baudrate() argument
255 module->hw->UART_CLOCK_SOURCE.reg = UART_CLOCK_SOURCE_CLOCK_SELECT_0; in uart_set_baudrate()
256 module->hw->UART_BAUD_RATE.reg = in uart_set_baudrate()
309 enum status_code uart_init(struct uart_module *const module, Uart * const hw, in uart_init() argument
313 Assert(module); in uart_init()
321 module->hw = hw; in uart_init()
324 module->callback[i] = NULL; in uart_init()
326 module->rx_buffer_ptr = NULL; in uart_init()
327 module->tx_buffer_ptr = NULL; in uart_init()
328 module->remaining_rx_buffer_length = 0; in uart_init()
329 module->remaining_tx_buffer_length = 0; in uart_init()
330 module->callback_reg_mask = 0; in uart_init()
331 module->callback_enable_mask = 0; in uart_init()
332 module->status = STATUS_OK; in uart_init()
339 _uart_instances[0] = module; in uart_init()
349 _uart_instances[1] = module; in uart_init()
373 while (module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) { in uart_init()
374 i = module->hw->RECEIVE_DATA.reg; in uart_init()
378 module->hw->UART_CONFIGURATION.reg = 0; in uart_init()
414 module->hw->UART_CONFIGURATION.reg = config_temp; in uart_init()
417 uart_set_baudrate(module, config->baud_rate); in uart_init()
419 module->hw->RX_INTERRUPT_MASK.reg = 0; // disable int at initialization, enable it at read time in uart_init()
420 module->hw->TX_INTERRUPT_MASK.reg = 0; // disable int at initialization, enable it at write time in uart_init()
437 enum status_code uart_write_wait(struct uart_module *const module, in uart_write_wait() argument
440 while (!(module->hw->TRANSMIT_STATUS.reg & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL)); in uart_write_wait()
442 module->hw->TRANSMIT_DATA.reg = tx_data; in uart_write_wait()
458 enum status_code uart_read_wait(struct uart_module *const module, in uart_read_wait() argument
461 while (!(module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)); in uart_read_wait()
463 *rx_data = module->hw->RECEIVE_DATA.reg; in uart_read_wait()
485 enum status_code uart_write_buffer_wait(struct uart_module *const module, in uart_write_buffer_wait() argument
489 uart_write_wait(module, *tx_data++); in uart_write_buffer_wait()
511 enum status_code uart_read_buffer_wait(struct uart_module *const module, in uart_read_buffer_wait() argument
515 uart_read_wait(module, rx_data++); in uart_read_buffer_wait()
530 struct uart_module *const module, in _uart_write_buffer() argument
534 Assert(module); in _uart_write_buffer()
538 module->remaining_tx_buffer_length = length; in _uart_write_buffer()
539 module->tx_buffer_ptr = tx_data; in _uart_write_buffer()
540 module->status = STATUS_BUSY; in _uart_write_buffer()
542 module->hw->TX_INTERRUPT_MASK.reg = UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK; in _uart_write_buffer()
555 struct uart_module *const module, in _uart_read_buffer() argument
559 Assert(module); in _uart_read_buffer()
564 module->remaining_rx_buffer_length = length; in _uart_read_buffer()
565 module->rx_buffer_ptr = rx_data; in _uart_read_buffer()
566 module->status = STATUS_BUSY; in _uart_read_buffer()
568 module->hw->RX_INTERRUPT_MASK.reg = UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK; in _uart_read_buffer()
587 enum status_code uart_write_buffer_job(struct uart_module *const module, in uart_write_buffer_job() argument
590 Assert(module); in uart_write_buffer_job()
598 if (module->status == STATUS_BUSY) { in uart_write_buffer_job()
603 _uart_write_buffer(module, tx_data, length); in uart_write_buffer_job()
629 enum status_code uart_read_buffer_job(struct uart_module *const module, in uart_read_buffer_job() argument
633 Assert(module); in uart_read_buffer_job()
641 if (module->status == STATUS_BUSY) { in uart_read_buffer_job()
646 _uart_read_buffer(module, rx_data, length); in uart_read_buffer_job()
664 void uart_register_callback(struct uart_module *const module, in uart_register_callback() argument
669 Assert(module); in uart_register_callback()
673 module->callback[callback_type] = callback_func; in uart_register_callback()
675 module->callback_reg_mask |= (1 << callback_type); in uart_register_callback()
687 void uart_unregister_callback(struct uart_module *module, in uart_unregister_callback() argument
691 Assert(module); in uart_unregister_callback()
694 module->callback[callback_type] = NULL; in uart_unregister_callback()
696 module->callback_reg_mask &= ~(1 << callback_type); in uart_unregister_callback()
709 void uart_enable_callback(struct uart_module *const module, in uart_enable_callback() argument
713 Assert(module); in uart_enable_callback()
716 module->callback_enable_mask |= (1 << callback_type); in uart_enable_callback()
719 module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK; in uart_enable_callback()
732 void uart_disable_callback(struct uart_module *const module, in uart_disable_callback() argument
736 Assert(module); in uart_disable_callback()
739 module->callback_enable_mask &= ~(1 << callback_type); in uart_disable_callback()
742 module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK; in uart_disable_callback()
752 void uart_enable_transmit_dma(struct uart_module *const module) in uart_enable_transmit_dma() argument
755 Assert(module); in uart_enable_transmit_dma()
758 module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK; in uart_enable_transmit_dma()
761 if (module->hw == UART0) { in uart_enable_transmit_dma()
763 } else if (module->hw == UART1) { in uart_enable_transmit_dma()
773 void uart_disable_transmit_dma(struct uart_module *const module) in uart_disable_transmit_dma() argument
776 Assert(module); in uart_disable_transmit_dma()
778 module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK; in uart_disable_transmit_dma()
781 if (module->hw == UART0) { in uart_disable_transmit_dma()
783 } else if (module->hw == UART1) { in uart_disable_transmit_dma()
793 void uart_enable_receive_dma(struct uart_module *const module) in uart_enable_receive_dma() argument
796 Assert(module); in uart_enable_receive_dma()
799 module->hw->RX_INTERRUPT_MASK.reg |= UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK; in uart_enable_receive_dma()
802 if (module->hw == UART0) { in uart_enable_receive_dma()
804 } else if (module->hw == UART1) { in uart_enable_receive_dma()
814 void uart_disable_receive_dma(struct uart_module *const module) in uart_disable_receive_dma() argument
817 Assert(module); in uart_disable_receive_dma()
819 module->hw->RX_INTERRUPT_MASK.reg &= ~UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK; in uart_disable_receive_dma()
822 if (module->hw == UART0) { in uart_disable_receive_dma()
824 } else if (module->hw == UART1) { in uart_disable_receive_dma()