Lines Matching refs:this_uart
74 static void global_init(mss_uart_instance_t * this_uart, uint32_t baud_rate,
76 static void MSS_UART_isr(mss_uart_instance_t * this_uart);
77 static void default_tx_handler(mss_uart_instance_t * this_uart);
81 mss_uart_instance_t * this_uart,
101 mss_uart_instance_t* this_uart, in MSS_UART_init() argument
108 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_init()
111 global_init(this_uart, baud_rate, line_config); in MSS_UART_init()
114 clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN); in MSS_UART_init()
117 clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD); in MSS_UART_init()
120 clear_bit_reg8(&this_uart->hw_reg->MM2, EERR); in MSS_UART_init()
123 this_uart->tx_handler = default_tx_handler; in MSS_UART_init()
131 mss_uart_instance_t* this_uart, in MSS_UART_lin_init() argument
138 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_lin_init()
141 global_init(this_uart, baud_rate, line_config); in MSS_UART_lin_init()
144 set_bit_reg8(&this_uart->hw_reg->MM0, ELIN); in MSS_UART_lin_init()
147 clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD); in MSS_UART_lin_init()
150 clear_bit_reg8(&this_uart->hw_reg->MM2, EERR); in MSS_UART_lin_init()
159 mss_uart_instance_t* this_uart, in MSS_UART_irda_init() argument
169 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_irda_init()
172 global_init(this_uart, baud_rate, line_config); in MSS_UART_irda_init()
175 clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN); in MSS_UART_irda_init()
178 set_bit_reg8(&this_uart->hw_reg->MM1, EIRD); in MSS_UART_irda_init()
179 ((rxpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EIRX) : in MSS_UART_irda_init()
180 set_bit_reg8(&this_uart->hw_reg->MM1,EIRX)); in MSS_UART_irda_init()
182 ((txpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITX) : in MSS_UART_irda_init()
183 set_bit_reg8(&this_uart->hw_reg->MM1,EITX)); in MSS_UART_irda_init()
185 ((pw == MSS_UART_3_BY_16) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITP) : in MSS_UART_irda_init()
186 set_bit_reg8(&this_uart->hw_reg->MM1,EITP)); in MSS_UART_irda_init()
188 clear_bit_reg8(&this_uart->hw_reg->MM2, EERR); in MSS_UART_irda_init()
197 mss_uart_instance_t* this_uart, in MSS_UART_smartcard_init() argument
204 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_smartcard_init()
207 global_init(this_uart, baud_rate, line_config); in MSS_UART_smartcard_init()
210 clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN); in MSS_UART_smartcard_init()
213 clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD); in MSS_UART_smartcard_init()
219 set_bit_reg8(&this_uart->hw_reg->MM2, EERR); in MSS_UART_smartcard_init()
221 set_bit_reg8(&this_uart->hw_reg->MM2,ESWM); in MSS_UART_smartcard_init()
231 mss_uart_instance_t * this_uart, in MSS_UART_polled_tx() argument
240 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_polled_tx()
244 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_polled_tx()
252 status = this_uart->hw_reg->LSR; in MSS_UART_polled_tx()
253 this_uart->status |= status; in MSS_UART_polled_tx()
270 this_uart->hw_reg->THR = pbuff[char_idx]; in MSS_UART_polled_tx()
287 mss_uart_instance_t * this_uart, in MSS_UART_polled_tx_string() argument
296 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_polled_tx_string()
299 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_polled_tx_string()
313 status = this_uart->hw_reg->LSR; in MSS_UART_polled_tx_string()
314 this_uart->status |= status; in MSS_UART_polled_tx_string()
324 this_uart->hw_reg->THR = data_byte; in MSS_UART_polled_tx_string()
340 mss_uart_instance_t * this_uart, in MSS_UART_irq_tx() argument
345 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_irq_tx()
350 ((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))) in MSS_UART_irq_tx()
353 this_uart->tx_buffer = pbuff; in MSS_UART_irq_tx()
354 this_uart->tx_buff_size = tx_size; in MSS_UART_irq_tx()
355 this_uart->tx_idx = (uint16_t)0; in MSS_UART_irq_tx()
358 NVIC_ClearPendingIRQ(this_uart->irqn); in MSS_UART_irq_tx()
361 this_uart->tx_handler = default_tx_handler; in MSS_UART_irq_tx()
364 set_bit_reg8(&this_uart->hw_reg->IER,ETBEI); in MSS_UART_irq_tx()
367 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_irq_tx()
377 mss_uart_instance_t * this_uart in MSS_UART_tx_complete() argument
383 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_tx_complete()
385 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_tx_complete()
388 status = this_uart->hw_reg->LSR; in MSS_UART_tx_complete()
389 this_uart->status |= status; in MSS_UART_tx_complete()
391 if((TX_COMPLETE == this_uart->tx_buff_size) && in MSS_UART_tx_complete()
407 mss_uart_instance_t * this_uart, in MSS_UART_get_rx() argument
415 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_get_rx()
419 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_get_rx()
422 status = this_uart->hw_reg->LSR; in MSS_UART_get_rx()
423 this_uart->status |= status; in MSS_UART_get_rx()
428 rx_buff[rx_size] = this_uart->hw_reg->RBR; in MSS_UART_get_rx()
430 status = this_uart->hw_reg->LSR; in MSS_UART_get_rx()
431 this_uart->status |= status; in MSS_UART_get_rx()
442 mss_uart_instance_t * this_uart, in MSS_UART_enable_irq() argument
446 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_enable_irq()
449 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_enable_irq()
453 NVIC_ClearPendingIRQ(this_uart->irqn); in MSS_UART_enable_irq()
461 this_uart->hw_reg->IER |= (uint8_t)irq_mask & IIRF_MASK; in MSS_UART_enable_irq()
470 this_uart->hw_reg->IEM |= (uint8_t)(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 4u); in MSS_UART_enable_irq()
473 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_enable_irq()
483 mss_uart_instance_t * this_uart, in MSS_UART_disable_irq() argument
487 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_disable_irq()
489 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_disable_irq()
497 this_uart->hw_reg->IER &= ((uint8_t)(~((uint32_t)irq_mask & (uint32_t)IIRF_MASK))); in MSS_UART_disable_irq()
506 this_uart->hw_reg->IEM |= (uint8_t)(~(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 8u)); in MSS_UART_disable_irq()
509 NVIC_ClearPendingIRQ(this_uart->irqn); in MSS_UART_disable_irq()
514 NVIC_DisableIRQ(this_uart->irqn); in MSS_UART_disable_irq()
526 mss_uart_instance_t * this_uart, in MSS_UART_set_rx_handler() argument
531 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_rx_handler()
535 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_rx_handler()
539 this_uart->rx_handler = handler; in MSS_UART_set_rx_handler()
542 this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR & in MSS_UART_set_rx_handler()
546 NVIC_ClearPendingIRQ(this_uart->irqn); in MSS_UART_set_rx_handler()
549 set_bit_reg8(&this_uart->hw_reg->IER,ERBFI); in MSS_UART_set_rx_handler()
552 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_rx_handler()
562 mss_uart_instance_t * this_uart, in MSS_UART_set_loopback() argument
566 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_loopback()
569 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) || in MSS_UART_set_loopback()
576 clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP); in MSS_UART_set_loopback()
581 set_bit_reg8(&this_uart->hw_reg->MCR,LOOP); in MSS_UART_set_loopback()
587 this_uart->hw_reg->MCR &= ~RLOOP_MASK; in MSS_UART_set_loopback()
592 this_uart->hw_reg->MCR |= (1u << RLOOP); in MSS_UART_set_loopback()
597 this_uart->hw_reg->MCR |= (1u << ECHO); in MSS_UART_set_loopback()
643 mss_uart_instance_t * this_uart, in MSS_UART_set_rxstatus_handler() argument
647 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_rxstatus_handler()
650 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_rxstatus_handler()
653 this_uart->linests_handler = handler; in MSS_UART_set_rxstatus_handler()
656 NVIC_ClearPendingIRQ(this_uart->irqn); in MSS_UART_set_rxstatus_handler()
659 set_bit_reg8(&this_uart->hw_reg->IER,ELSI); in MSS_UART_set_rxstatus_handler()
662 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_rxstatus_handler()
672 mss_uart_instance_t * this_uart, in MSS_UART_set_tx_handler() argument
676 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_tx_handler()
679 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_tx_handler()
682 this_uart->tx_handler = handler; in MSS_UART_set_tx_handler()
685 this_uart->tx_buffer = (const uint8_t *)0; in MSS_UART_set_tx_handler()
686 this_uart->tx_buff_size = 0u; in MSS_UART_set_tx_handler()
689 NVIC_ClearPendingIRQ(this_uart->irqn); in MSS_UART_set_tx_handler()
692 set_bit_reg8(&this_uart->hw_reg->IER,ETBEI); in MSS_UART_set_tx_handler()
695 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_tx_handler()
705 mss_uart_instance_t * this_uart, in MSS_UART_set_modemstatus_handler() argument
709 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_modemstatus_handler()
712 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_modemstatus_handler()
715 this_uart->modemsts_handler = handler; in MSS_UART_set_modemstatus_handler()
718 NVIC_ClearPendingIRQ(this_uart->irqn); in MSS_UART_set_modemstatus_handler()
721 set_bit_reg8(&this_uart->hw_reg->IER,EDSSI); in MSS_UART_set_modemstatus_handler()
724 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_modemstatus_handler()
734 mss_uart_instance_t * this_uart, in MSS_UART_fill_tx_fifo() argument
742 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_fill_tx_fifo()
748 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_fill_tx_fifo()
752 status = this_uart->hw_reg->LSR; in MSS_UART_fill_tx_fifo()
753 this_uart->status |= status; in MSS_UART_fill_tx_fifo()
768 this_uart->hw_reg->THR = tx_buffer[size_sent]; in MSS_UART_fill_tx_fifo()
781 mss_uart_instance_t * this_uart in MSS_UART_get_rx_status() argument
786 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_get_rx_status()
788 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_get_rx_status()
798 this_uart->status |= (this_uart->hw_reg->LSR); in MSS_UART_get_rx_status()
799 status = (this_uart->status & STATUS_ERROR_MASK); in MSS_UART_get_rx_status()
801 this_uart->status = 0u; in MSS_UART_get_rx_status()
812 mss_uart_instance_t * this_uart in MSS_UART_get_modem_status() argument
817 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_get_modem_status()
819 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_get_modem_status()
832 status = this_uart->hw_reg->MSR; in MSS_UART_get_modem_status()
844 mss_uart_instance_t * this_uart in MSS_UART_get_tx_status() argument
849 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_get_tx_status()
851 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_get_tx_status()
854 status = this_uart->hw_reg->LSR; in MSS_UART_get_tx_status()
855 this_uart->status |= status; in MSS_UART_get_tx_status()
872 mss_uart_instance_t * this_uart in MSS_UART_set_break() argument
875 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_break()
876 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_set_break()
879 set_bit_reg8(&this_uart->hw_reg->LCR,SB); in MSS_UART_set_break()
889 mss_uart_instance_t * this_uart in MSS_UART_clear_break() argument
892 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_clear_break()
893 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_clear_break()
896 clear_bit_reg8(&this_uart->hw_reg->LCR,SB); in MSS_UART_clear_break()
906 mss_uart_instance_t * this_uart, in MSS_UART_set_pidpei_handler() argument
910 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_pidpei_handler()
913 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_pidpei_handler()
916 this_uart->pid_pei_handler = handler; in MSS_UART_set_pidpei_handler()
919 NVIC_ClearPendingIRQ( this_uart->irqn ); in MSS_UART_set_pidpei_handler()
922 set_bit_reg8(&this_uart->hw_reg->IEM,EPID_PEI); in MSS_UART_set_pidpei_handler()
925 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_pidpei_handler()
935 mss_uart_instance_t * this_uart, in MSS_UART_set_linbreak_handler() argument
939 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_linbreak_handler()
942 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_linbreak_handler()
945 this_uart->break_handler = handler; in MSS_UART_set_linbreak_handler()
948 NVIC_ClearPendingIRQ( this_uart->irqn ); in MSS_UART_set_linbreak_handler()
951 set_bit_reg8(&this_uart->hw_reg->IEM,ELINBI); in MSS_UART_set_linbreak_handler()
954 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_linbreak_handler()
964 mss_uart_instance_t * this_uart, in MSS_UART_set_linsync_handler() argument
968 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_linsync_handler()
971 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_linsync_handler()
974 this_uart->sync_handler = handler; in MSS_UART_set_linsync_handler()
977 NVIC_ClearPendingIRQ( this_uart->irqn ); in MSS_UART_set_linsync_handler()
980 set_bit_reg8(&this_uart->hw_reg->IEM,ELINSI); in MSS_UART_set_linsync_handler()
983 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_linsync_handler()
993 mss_uart_instance_t * this_uart, in MSS_UART_set_nack_handler() argument
997 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_nack_handler()
1000 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_nack_handler()
1003 this_uart->nack_handler = handler; in MSS_UART_set_nack_handler()
1006 NVIC_ClearPendingIRQ( this_uart->irqn ); in MSS_UART_set_nack_handler()
1009 set_bit_reg8(&this_uart->hw_reg->IEM,ENACKI); in MSS_UART_set_nack_handler()
1012 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_nack_handler()
1022 mss_uart_instance_t * this_uart, in MSS_UART_set_rx_timeout_handler() argument
1026 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_rx_timeout_handler()
1029 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_rx_timeout_handler()
1032 this_uart->rto_handler = handler; in MSS_UART_set_rx_timeout_handler()
1035 NVIC_ClearPendingIRQ( this_uart->irqn ); in MSS_UART_set_rx_timeout_handler()
1038 set_bit_reg8(&this_uart->hw_reg->IEM,ERTOI); in MSS_UART_set_rx_timeout_handler()
1041 NVIC_EnableIRQ(this_uart->irqn); in MSS_UART_set_rx_timeout_handler()
1051 mss_uart_instance_t * this_uart in MSS_UART_enable_half_duplex() argument
1054 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_enable_half_duplex()
1055 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_enable_half_duplex()
1058 set_bit_reg8(&this_uart->hw_reg->MM2,ESWM); in MSS_UART_enable_half_duplex()
1068 mss_uart_instance_t * this_uart in MSS_UART_disable_half_duplex() argument
1071 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_disable_half_duplex()
1072 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_disable_half_duplex()
1075 clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM); in MSS_UART_disable_half_duplex()
1085 mss_uart_instance_t * this_uart, in MSS_UART_set_rx_endian() argument
1089 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_rx_endian()
1092 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_rx_endian()
1096 ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)) : in MSS_UART_set_rx_endian()
1097 (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX))); in MSS_UART_set_rx_endian()
1107 mss_uart_instance_t * this_uart, in MSS_UART_set_tx_endian() argument
1111 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_tx_endian()
1114 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_tx_endian()
1118 ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) : in MSS_UART_set_tx_endian()
1119 (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) ) ; in MSS_UART_set_tx_endian()
1129 mss_uart_instance_t * this_uart, in MSS_UART_set_filter_length() argument
1133 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_filter_length()
1136 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_filter_length()
1140 this_uart->hw_reg->GFR = (uint8_t)length; in MSS_UART_set_filter_length()
1150 mss_uart_instance_t * this_uart in MSS_UART_enable_afm() argument
1153 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_enable_afm()
1155 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_enable_afm()
1158 set_bit_reg8(&this_uart->hw_reg->MM2,EAFM); in MSS_UART_enable_afm()
1168 mss_uart_instance_t * this_uart in MSS_UART_disable_afm() argument
1171 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_disable_afm()
1173 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_disable_afm()
1177 clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM); in MSS_UART_disable_afm()
1187 mss_uart_instance_t * this_uart in MSS_UART_enable_afclear() argument
1190 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_enable_afclear()
1192 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_enable_afclear()
1197 set_bit_reg8(&this_uart->hw_reg->MM2,EAFC); in MSS_UART_enable_afclear()
1207 mss_uart_instance_t * this_uart in MSS_UART_disable_afclear() argument
1210 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_disable_afclear()
1212 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_disable_afclear()
1215 clear_bit_reg8(&this_uart->hw_reg->MM2,EAFC); in MSS_UART_disable_afclear()
1225 mss_uart_instance_t * this_uart, in MSS_UART_enable_rx_timeout() argument
1229 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_enable_rx_timeout()
1231 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_enable_rx_timeout()
1234 this_uart->hw_reg->RTO = timeout; in MSS_UART_enable_rx_timeout()
1236 set_bit_reg8(&this_uart->hw_reg->MM0,ERTO); in MSS_UART_enable_rx_timeout()
1246 mss_uart_instance_t * this_uart in MSS_UART_disable_rx_timeout() argument
1249 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_disable_rx_timeout()
1251 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_disable_rx_timeout()
1254 clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO); in MSS_UART_disable_rx_timeout()
1264 mss_uart_instance_t * this_uart, in MSS_UART_enable_tx_time_guard() argument
1268 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_enable_tx_time_guard()
1270 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_enable_tx_time_guard()
1273 this_uart->hw_reg->TTG = timeguard; in MSS_UART_enable_tx_time_guard()
1275 set_bit_reg8(&this_uart->hw_reg->MM0,ETTG); in MSS_UART_enable_tx_time_guard()
1285 mss_uart_instance_t * this_uart in MSS_UART_disable_tx_time_guard() argument
1288 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_disable_tx_time_guard()
1290 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_disable_tx_time_guard()
1293 clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); in MSS_UART_disable_tx_time_guard()
1303 mss_uart_instance_t * this_uart, in MSS_UART_set_address() argument
1307 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_address()
1309 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_set_address()
1311 this_uart->hw_reg->ADR = address; in MSS_UART_set_address()
1321 mss_uart_instance_t * this_uart, in MSS_UART_set_ready_mode() argument
1325 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_ready_mode()
1328 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_ready_mode()
1332 ((MSS_UART_READY_MODE0 == mode) ? clear_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) : in MSS_UART_set_ready_mode()
1333 set_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) ); in MSS_UART_set_ready_mode()
1343 mss_uart_instance_t * this_uart, in config_baud_divisors() argument
1347 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in config_baud_divisors()
1349 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in config_baud_divisors()
1357 this_uart->baudrate = baudrate; in config_baud_divisors()
1362 if(this_uart == &g_mss_uart0) in config_baud_divisors()
1393 set_bit_reg8(&this_uart->hw_reg->LCR,DLAB); in config_baud_divisors()
1396 this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8); in config_baud_divisors()
1398 this_uart->hw_reg->DLR = (uint8_t)baud_value; in config_baud_divisors()
1401 clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB); in config_baud_divisors()
1404 set_bit_reg8(&this_uart->hw_reg->MM0,EFBR); in config_baud_divisors()
1408 this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value; in config_baud_divisors()
1416 set_bit_reg8(&this_uart->hw_reg->LCR,DLAB); in config_baud_divisors()
1419 this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u); in config_baud_divisors()
1421 this_uart->hw_reg->DLR = (uint8_t)baud_value; in config_baud_divisors()
1424 clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB); in config_baud_divisors()
1427 clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR); in config_baud_divisors()
1439 mss_uart_instance_t * this_uart, in MSS_UART_set_usart_mode() argument
1443 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_set_usart_mode()
1446 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in MSS_UART_set_usart_mode()
1451 this_uart->hw_reg->MM0 &= ~SYNC_ASYNC_MODE_MASK; in MSS_UART_set_usart_mode()
1452 this_uart->hw_reg->MM0 |= (uint8_t)mode; in MSS_UART_set_usart_mode()
1464 mss_uart_instance_t * this_uart, in global_init() argument
1471 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in global_init()
1473 if(this_uart == &g_mss_uart0) in global_init()
1475 this_uart->hw_reg = UART0; in global_init()
1476 this_uart->irqn = UART0_IRQn; in global_init()
1486 this_uart->hw_reg = UART1; in global_init()
1487 this_uart->irqn = UART1_IRQn; in global_init()
1497 this_uart->hw_reg->IER = 0u; in global_init()
1500 this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE; in global_init()
1502 set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_RX_FIFO); in global_init()
1504 set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_TX_FIFO); in global_init()
1509 set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN); in global_init()
1512 clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP); in global_init()
1513 clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP); in global_init()
1516 clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX); in global_init()
1518 clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX); in global_init()
1521 clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM); in global_init()
1524 clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); in global_init()
1527 clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO); in global_init()
1530 clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR); in global_init()
1533 clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM); in global_init()
1536 this_uart->hw_reg->GFR = 0u; in global_init()
1538 this_uart->hw_reg->TTG = 0u; in global_init()
1540 this_uart->hw_reg->RTO = 0u; in global_init()
1546 config_baud_divisors(this_uart, baud_rate); in global_init()
1549 this_uart->hw_reg->LCR = line_config; in global_init()
1552 this_uart->baudrate = baud_rate; in global_init()
1553 this_uart->lineconfig = line_config; in global_init()
1554 this_uart->tx_buff_size = TX_COMPLETE; in global_init()
1555 this_uart->tx_buffer = (const uint8_t *)0; in global_init()
1556 this_uart->tx_idx = 0u; in global_init()
1559 this_uart->rx_handler = NULL_HANDLER; in global_init()
1560 this_uart->tx_handler = NULL_HANDLER; in global_init()
1561 this_uart->linests_handler = NULL_HANDLER; in global_init()
1562 this_uart->modemsts_handler = NULL_HANDLER; in global_init()
1563 this_uart->rto_handler = NULL_HANDLER; in global_init()
1564 this_uart->nack_handler = NULL_HANDLER; in global_init()
1565 this_uart->pid_pei_handler = NULL_HANDLER; in global_init()
1566 this_uart->break_handler = NULL_HANDLER; in global_init()
1567 this_uart->sync_handler = NULL_HANDLER; in global_init()
1570 this_uart->status = 0u; in global_init()
1584 mss_uart_instance_t * this_uart in MSS_UART_isr() argument
1589 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in MSS_UART_isr()
1591 if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) in MSS_UART_isr()
1593 iirf = this_uart->hw_reg->IIR & IIRF_MASK; in MSS_UART_isr()
1599 ASSERT(NULL_HANDLER != this_uart->modemsts_handler); in MSS_UART_isr()
1600 if(NULL_HANDLER != this_uart->modemsts_handler) in MSS_UART_isr()
1602 (*(this_uart->modemsts_handler))(this_uart); in MSS_UART_isr()
1609 ASSERT(NULL_HANDLER != this_uart->tx_handler); in MSS_UART_isr()
1610 if(NULL_HANDLER != this_uart->tx_handler) in MSS_UART_isr()
1612 (*(this_uart->tx_handler))(this_uart); in MSS_UART_isr()
1620 ASSERT(NULL_HANDLER != this_uart->rx_handler); in MSS_UART_isr()
1621 if(NULL_HANDLER != this_uart->rx_handler) in MSS_UART_isr()
1623 (*(this_uart->rx_handler))(this_uart); in MSS_UART_isr()
1630 ASSERT(NULL_HANDLER != this_uart->linests_handler); in MSS_UART_isr()
1631 if(NULL_HANDLER != this_uart->linests_handler) in MSS_UART_isr()
1633 (*(this_uart->linests_handler))(this_uart); in MSS_UART_isr()
1643 if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI)) in MSS_UART_isr()
1645 ASSERT(NULL_HANDLER != this_uart->rto_handler); in MSS_UART_isr()
1646 if(NULL_HANDLER != this_uart->rto_handler) in MSS_UART_isr()
1648 (*(this_uart->rto_handler))(this_uart); in MSS_UART_isr()
1652 if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI)) in MSS_UART_isr()
1654 ASSERT(NULL_HANDLER != this_uart->nack_handler); in MSS_UART_isr()
1655 if(NULL_HANDLER != this_uart->nack_handler) in MSS_UART_isr()
1657 (*(this_uart->nack_handler))(this_uart); in MSS_UART_isr()
1662 if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI)) in MSS_UART_isr()
1664 ASSERT(NULL_HANDLER != this_uart->pid_pei_handler); in MSS_UART_isr()
1665 if(NULL_HANDLER != this_uart->pid_pei_handler) in MSS_UART_isr()
1667 (*(this_uart->pid_pei_handler))(this_uart); in MSS_UART_isr()
1672 if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI)) in MSS_UART_isr()
1674 ASSERT(NULL_HANDLER != this_uart->break_handler); in MSS_UART_isr()
1675 if(NULL_HANDLER != this_uart->break_handler) in MSS_UART_isr()
1677 (*(this_uart->break_handler))(this_uart); in MSS_UART_isr()
1682 if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI)) in MSS_UART_isr()
1684 ASSERT(NULL_HANDLER != this_uart->sync_handler); in MSS_UART_isr()
1685 if(NULL_HANDLER != this_uart->sync_handler) in MSS_UART_isr()
1687 (*(this_uart->sync_handler))(this_uart); in MSS_UART_isr()
1708 mss_uart_instance_t * this_uart in default_tx_handler() argument
1713 ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); in default_tx_handler()
1714 ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer); in default_tx_handler()
1715 ASSERT(0u < this_uart->tx_buff_size); in default_tx_handler()
1717 if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && in default_tx_handler()
1718 (((uint8_t *)0 ) != this_uart->tx_buffer) && in default_tx_handler()
1719 (0u < this_uart->tx_buff_size)) in default_tx_handler()
1722 status = this_uart->hw_reg->LSR; in default_tx_handler()
1723 this_uart->status |= status; in default_tx_handler()
1733 uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx; in default_tx_handler()
1745 this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx]; in default_tx_handler()
1746 ++this_uart->tx_idx; in default_tx_handler()
1751 if(this_uart->tx_idx == this_uart->tx_buff_size) in default_tx_handler()
1753 this_uart->tx_buff_size = TX_COMPLETE; in default_tx_handler()
1755 clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI); in default_tx_handler()