Lines Matching refs:bit
55 uart->sci_regs->SCICTL2.bit.TXINTENA = 1; in c28x_configure()
56 uart->sci_regs->SCICTL2.bit.RXBKINTENA = 1; in c28x_configure()
66 uart->sci_regs->SCICCR.bit.SCICHAR = 4; in c28x_configure()
69 uart->sci_regs->SCICCR.bit.SCICHAR = 5; in c28x_configure()
72 uart->sci_regs->SCICCR.bit.SCICHAR = 6; in c28x_configure()
75 uart->sci_regs->SCICCR.bit.SCICHAR = 7; in c28x_configure()
78 uart->sci_regs->SCICCR.bit.SCICHAR = 7; in c28x_configure()
84 uart->sci_regs->SCICCR.bit.STOPBITS = 0; in c28x_configure()
87 uart->sci_regs->SCICCR.bit.STOPBITS = 1; in c28x_configure()
90 uart->sci_regs->SCICCR.bit.STOPBITS = 0; in c28x_configure()
96 uart->sci_regs->SCICCR.bit.PARITYENA = 0; in c28x_configure()
99 uart->sci_regs->SCICCR.bit.PARITYENA = 1; in c28x_configure()
100 uart->sci_regs->SCICCR.bit.PARITY = 0; in c28x_configure()
103 uart->sci_regs->SCICCR.bit.PARITYENA = 1; in c28x_configure()
104 uart->sci_regs->SCICCR.bit.PARITY = 1; in c28x_configure()
107 uart->sci_regs->SCICCR.bit.PARITYENA = 0; in c28x_configure()
128 uart->sci_regs->SCICTL2.bit.TXINTENA = 0; in c28x_control()
129 uart->sci_regs->SCICTL2.bit.RXBKINTENA = 0; in c28x_control()
134 uart->sci_regs->SCICTL2.bit.TXINTENA = 1; in c28x_control()
135 uart->sci_regs->SCICTL2.bit.RXBKINTENA = 1; in c28x_control()
167 SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag in uart_isr()
199 GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; in rt_hw_sci_init()
200 GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; in rt_hw_sci_init()
201 GpioCtrlRegs.GPBGMUX1.bit.GPIO42 = 3; in rt_hw_sci_init()
202 GpioCtrlRegs.GPBGMUX1.bit.GPIO43 = 3; in rt_hw_sci_init()
204 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; in rt_hw_sci_init()
205 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; in rt_hw_sci_init()
206 GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0; in rt_hw_sci_init()
207 GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 0; in rt_hw_sci_init()
209 GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 2; in rt_hw_sci_init()
210 GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 2; in rt_hw_sci_init()
211 GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; in rt_hw_sci_init()
212 GpioCtrlRegs.GPEGMUX1.bit.GPIO139 = 1; in rt_hw_sci_init()
214 CpuSysRegs.PCLKCR7.bit.SCI_A = 1; in rt_hw_sci_init()
215 CpuSysRegs.PCLKCR7.bit.SCI_B = 1; in rt_hw_sci_init()
216 CpuSysRegs.PCLKCR7.bit.SCI_C = 1; in rt_hw_sci_init()
225 PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block in rt_hw_sci_init()
226 PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // PIE Group 9, INT1 in rt_hw_sci_init()