Lines Matching refs:ui32Base
107 _I2CBaseValid(uint32_t ui32Base) in _I2CBaseValid() argument
109 return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) || in _I2CBaseValid()
110 (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) || in _I2CBaseValid()
111 (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) || in _I2CBaseValid()
112 (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) || in _I2CBaseValid()
113 (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE)); in _I2CBaseValid()
131 _I2CIntNumberGet(uint32_t ui32Base) in _I2CIntNumberGet() argument
139 ASSERT(_I2CBaseValid(ui32Base)); in _I2CIntNumberGet()
159 if(ppui32I2CIntMap[i8Idx][0] == ui32Base) in _I2CIntNumberGet()
204 I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, in I2CMasterInitExpClk() argument
213 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterInitExpClk()
218 I2CMasterEnable(ui32Base); in I2CMasterInitExpClk()
240 HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; in I2CMasterInitExpClk()
246 if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) in I2CMasterInitExpClk()
250 HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; in I2CMasterInitExpClk()
271 I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) in I2CSlaveInit() argument
276 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveInit()
282 I2CSlaveEnable(ui32Base); in I2CSlaveInit()
287 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; in I2CSlaveInit()
309 I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) in I2CSlaveAddressSet() argument
314 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveAddressSet()
328 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; in I2CSlaveAddressSet()
337 HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; in I2CSlaveAddressSet()
355 I2CMasterEnable(uint32_t ui32Base) in I2CMasterEnable() argument
360 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterEnable()
365 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; in I2CMasterEnable()
380 I2CSlaveEnable(uint32_t ui32Base) in I2CSlaveEnable() argument
385 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveEnable()
390 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; in I2CSlaveEnable()
395 HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; in I2CSlaveEnable()
410 I2CMasterDisable(uint32_t ui32Base) in I2CMasterDisable() argument
415 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterDisable()
420 HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); in I2CMasterDisable()
435 I2CSlaveDisable(uint32_t ui32Base) in I2CSlaveDisable() argument
440 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveDisable()
445 HWREG(ui32Base + I2C_O_SCSR) = 0; in I2CSlaveDisable()
450 HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); in I2CSlaveDisable()
475 I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) in I2CIntRegister() argument
482 ASSERT(_I2CBaseValid(ui32Base)); in I2CIntRegister()
487 ui32Int = _I2CIntNumberGet(ui32Base); in I2CIntRegister()
519 I2CIntUnregister(uint32_t ui32Base) in I2CIntUnregister() argument
526 ASSERT(_I2CBaseValid(ui32Base)); in I2CIntUnregister()
531 ui32Int = _I2CIntNumberGet(ui32Base); in I2CIntUnregister()
558 I2CMasterIntEnable(uint32_t ui32Base) in I2CMasterIntEnable() argument
563 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntEnable()
568 HWREG(ui32Base + I2C_O_MIMR) = 1; in I2CMasterIntEnable()
605 I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CMasterIntEnableEx() argument
610 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntEnableEx()
615 HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; in I2CMasterIntEnableEx()
630 I2CSlaveIntEnable(uint32_t ui32Base) in I2CSlaveIntEnable() argument
635 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntEnable()
640 HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; in I2CSlaveIntEnable()
674 I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CSlaveIntEnableEx() argument
679 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntEnableEx()
684 HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; in I2CSlaveIntEnableEx()
699 I2CMasterIntDisable(uint32_t ui32Base) in I2CMasterIntDisable() argument
704 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntDisable()
709 HWREG(ui32Base + I2C_O_MIMR) = 0; in I2CMasterIntDisable()
731 I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CMasterIntDisableEx() argument
736 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntDisableEx()
741 HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; in I2CMasterIntDisableEx()
756 I2CSlaveIntDisable(uint32_t ui32Base) in I2CSlaveIntDisable() argument
761 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntDisable()
766 HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; in I2CSlaveIntDisable()
788 I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CSlaveIntDisableEx() argument
793 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntDisableEx()
798 HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; in I2CSlaveIntDisableEx()
818 I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) in I2CMasterIntStatus() argument
823 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntStatus()
831 return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); in I2CMasterIntStatus()
835 return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); in I2CMasterIntStatus()
856 I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) in I2CMasterIntStatusEx() argument
861 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntStatusEx()
869 return(HWREG(ui32Base + I2C_O_MMIS)); in I2CMasterIntStatusEx()
873 return(HWREG(ui32Base + I2C_O_MRIS)); in I2CMasterIntStatusEx()
894 I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) in I2CSlaveIntStatus() argument
899 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntStatus()
907 return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); in I2CSlaveIntStatus()
911 return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); in I2CSlaveIntStatus()
932 I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) in I2CSlaveIntStatusEx() argument
937 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntStatusEx()
945 return(HWREG(ui32Base + I2C_O_SMIS)); in I2CSlaveIntStatusEx()
949 return(HWREG(ui32Base + I2C_O_SRIS)); in I2CSlaveIntStatusEx()
976 I2CMasterIntClear(uint32_t ui32Base) in I2CMasterIntClear() argument
981 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntClear()
986 HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; in I2CMasterIntClear()
993 HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; in I2CMasterIntClear()
1023 I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CMasterIntClearEx() argument
1028 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntClearEx()
1033 HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; in I2CMasterIntClearEx()
1059 I2CSlaveIntClear(uint32_t ui32Base) in I2CSlaveIntClear() argument
1064 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntClear()
1069 HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; in I2CSlaveIntClear()
1099 I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CSlaveIntClearEx() argument
1104 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntClearEx()
1109 HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; in I2CSlaveIntClearEx()
1130 I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, in I2CMasterSlaveAddrSet() argument
1136 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterSlaveAddrSet()
1142 HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; in I2CMasterSlaveAddrSet()
1162 I2CMasterLineStateGet(uint32_t ui32Base) in I2CMasterLineStateGet() argument
1167 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterLineStateGet()
1172 return(HWREG(ui32Base + I2C_O_MBMON)); in I2CMasterLineStateGet()
1189 I2CMasterBusy(uint32_t ui32Base) in I2CMasterBusy() argument
1194 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterBusy()
1199 if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) in I2CMasterBusy()
1224 I2CMasterBusBusy(uint32_t ui32Base) in I2CMasterBusBusy() argument
1229 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterBusBusy()
1234 if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) in I2CMasterBusBusy()
1286 I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) in I2CMasterControl() argument
1291 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterControl()
1318 HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; in I2CMasterControl()
1336 I2CMasterErr(uint32_t ui32Base) in I2CMasterErr() argument
1343 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterErr()
1348 ui32Err = HWREG(ui32Base + I2C_O_MCS); in I2CMasterErr()
1385 I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) in I2CMasterDataPut() argument
1390 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterDataPut()
1395 HWREG(ui32Base + I2C_O_MDR) = ui8Data; in I2CMasterDataPut()
1411 I2CMasterDataGet(uint32_t ui32Base) in I2CMasterDataGet() argument
1416 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterDataGet()
1421 return(HWREG(ui32Base + I2C_O_MDR)); in I2CMasterDataGet()
1444 I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) in I2CMasterTimeoutSet() argument
1449 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterTimeoutSet()
1454 HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; in I2CMasterTimeoutSet()
1474 I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) in I2CSlaveACKOverride() argument
1479 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveACKOverride()
1486 HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; in I2CSlaveACKOverride()
1490 HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; in I2CSlaveACKOverride()
1509 I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) in I2CSlaveACKValueSet() argument
1514 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveACKValueSet()
1521 HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; in I2CSlaveACKValueSet()
1525 HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; in I2CSlaveACKValueSet()
1563 I2CSlaveStatus(uint32_t ui32Base) in I2CSlaveStatus() argument
1568 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveStatus()
1573 return(HWREG(ui32Base + I2C_O_SCSR)); in I2CSlaveStatus()
1589 I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) in I2CSlaveDataPut() argument
1594 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveDataPut()
1599 HWREG(ui32Base + I2C_O_SDR) = ui8Data; in I2CSlaveDataPut()
1615 I2CSlaveDataGet(uint32_t ui32Base) in I2CSlaveDataGet() argument
1620 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveDataGet()
1625 return(HWREG(ui32Base + I2C_O_SDR)); in I2CSlaveDataGet()
1657 I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) in I2CTxFIFOConfigSet() argument
1662 ASSERT(_I2CBaseValid(ui32Base)); in I2CTxFIFOConfigSet()
1667 HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; in I2CTxFIFOConfigSet()
1672 HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; in I2CTxFIFOConfigSet()
1690 I2CTxFIFOFlush(uint32_t ui32Base) in I2CTxFIFOFlush() argument
1695 ASSERT(_I2CBaseValid(ui32Base)); in I2CTxFIFOFlush()
1700 HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; in I2CTxFIFOFlush()
1731 I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) in I2CRxFIFOConfigSet() argument
1736 ASSERT(_I2CBaseValid(ui32Base)); in I2CRxFIFOConfigSet()
1741 HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; in I2CRxFIFOConfigSet()
1746 HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; in I2CRxFIFOConfigSet()
1764 I2CRxFIFOFlush(uint32_t ui32Base) in I2CRxFIFOFlush() argument
1769 ASSERT(_I2CBaseValid(ui32Base)); in I2CRxFIFOFlush()
1774 HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; in I2CRxFIFOFlush()
1797 I2CFIFOStatus(uint32_t ui32Base) in I2CFIFOStatus() argument
1802 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFOStatus()
1807 return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); in I2CFIFOStatus()
1828 I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) in I2CFIFODataPut() argument
1833 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataPut()
1838 while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) in I2CFIFODataPut()
1845 HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; in I2CFIFODataPut()
1865 I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) in I2CFIFODataPutNonBlocking() argument
1870 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataPutNonBlocking()
1875 if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) in I2CFIFODataPutNonBlocking()
1881 HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; in I2CFIFODataPutNonBlocking()
1903 I2CFIFODataGet(uint32_t ui32Base) in I2CFIFODataGet() argument
1908 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataGet()
1913 while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) in I2CFIFODataGet()
1920 return(HWREG(ui32Base + I2C_O_FIFODATA)); in I2CFIFODataGet()
1941 I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) in I2CFIFODataGetNonBlocking() argument
1946 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataGetNonBlocking()
1951 if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) in I2CFIFODataGetNonBlocking()
1957 *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); in I2CFIFODataGetNonBlocking()
1983 I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) in I2CMasterBurstLengthSet() argument
1988 ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 256)); in I2CMasterBurstLengthSet()
1993 HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; in I2CMasterBurstLengthSet()
2014 I2CMasterBurstCountGet(uint32_t ui32Base) in I2CMasterBurstCountGet() argument
2019 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterBurstCountGet()
2024 return(HWREG(ui32Base + I2C_O_MBCNT)); in I2CMasterBurstCountGet()
2058 I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) in I2CMasterGlitchFilterConfigSet() argument
2063 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterGlitchFilterConfigSet()
2070 HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; in I2CMasterGlitchFilterConfigSet()
2081 HWREG(ui32Base + I2C_O_MCR2) |= (ui32Config >> 12); in I2CMasterGlitchFilterConfigSet()
2086 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_GFE; in I2CMasterGlitchFilterConfigSet()
2117 I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) in I2CSlaveFIFOEnable() argument
2122 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveFIFOEnable()
2127 HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; in I2CSlaveFIFOEnable()
2146 I2CSlaveFIFODisable(uint32_t ui32Base) in I2CSlaveFIFODisable() argument
2151 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveFIFODisable()
2156 HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; in I2CSlaveFIFODisable()
2175 void I2CLoopbackEnable(uint32_t ui32Base) in I2CLoopbackEnable() argument
2180 ASSERT(_I2CBaseValid(ui32Base)); in I2CLoopbackEnable()
2185 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_LPBK; in I2CLoopbackEnable()