Lines Matching refs:msgctl
61 rt_uint16_t msgctl; in msix_update_ctrl() local
63 rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); in msix_update_ctrl()
64 msgctl &= ~clear; in msix_update_ctrl()
65 msgctl |= set; in msix_update_ctrl()
66 rt_pci_write_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, msgctl); in msix_update_ctrl()
114 rt_uint16_t msgctl; in msi_write_enable() local
116 rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); in msi_write_enable()
118 msgctl &= ~PCIM_MSICTRL_MSI_ENABLE; in msi_write_enable()
122 msgctl |= PCIM_MSICTRL_MSI_ENABLE; in msi_write_enable()
125 rt_pci_write_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, msgctl); in msi_write_enable()
263 rt_uint32_t msgctl; in rt_pci_msi_write_msg() local
266 msgctl = msix->msg_ctrl; in rt_pci_msi_write_msg()
267 unmasked = !(msgctl & PCIM_MSIX_ENTRYVECTOR_CTRL_MASK); in rt_pci_msi_write_msg()
272 msix_write_vector_ctrl(msix, msgctl | PCIM_MSIX_ENTRYVECTOR_CTRL_MASK); in rt_pci_msi_write_msg()
281 msix_write_vector_ctrl(msix, msgctl); in rt_pci_msi_write_msg()
289 rt_uint16_t msgctl; in rt_pci_msi_write_msg() local
293 rt_pci_read_config_u16(pdev, pos + PCIR_MSI_CTRL, &msgctl); in rt_pci_msi_write_msg()
294 msgctl &= ~PCIM_MSICTRL_MME_MASK; in rt_pci_msi_write_msg()
295 msgctl |= msi->cap.multi_msg_use << PCIM_MSICTRL_MME_SHIFT; in rt_pci_msi_write_msg()
296 rt_pci_write_config_u16(pdev, pos + PCIR_MSI_CTRL, msgctl); in rt_pci_msi_write_msg()
320 rt_pci_read_config_u16(pdev, pos + PCIR_MSI_CTRL, &msgctl); in rt_pci_msi_write_msg()
505 rt_uint16_t msgctl; in rt_pci_msi_vector_count() local
517 rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); in rt_pci_msi_vector_count()
519 return 1 << ((msgctl & PCIM_MSICTRL_MMC_MASK) >> 1); in rt_pci_msi_vector_count()
546 rt_uint16_t msgctl; in msi_setup_msi_desc() local
555 rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); in msi_setup_msi_desc()
557 desc.msi.cap.is_64bit = !!(msgctl & PCIM_MSICTRL_64BIT); in msi_setup_msi_desc()
558 desc.msi.cap.is_masking = !!(msgctl & PCIM_MSICTRL_VECTOR); in msi_setup_msi_desc()
559 desc.msi.cap.multi_msg_max = (msgctl & PCIM_MSICTRL_MMC_MASK) >> 1; in msi_setup_msi_desc()
696 rt_uint16_t msgctl; in rt_pci_msix_vector_count() local
708 rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); in rt_pci_msix_vector_count()
710 return rt_pci_msix_table_size(msgctl); in rt_pci_msix_vector_count()
794 rt_uint16_t msgctl; in msix_capability_init() local
808 rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); in msix_capability_init()
810 table_size = rt_pci_msix_table_size(msgctl); in msix_capability_init()