Lines Matching refs:pdev
58 static void msix_update_ctrl(struct rt_pci_device *pdev, in msix_update_ctrl() argument
63 rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); in msix_update_ctrl()
66 rt_pci_write_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, msgctl); in msix_update_ctrl()
86 rt_uint32_t clear, rt_uint32_t set, struct rt_pci_device *pdev) in msi_write_mask() argument
90 rt_ubase_t level = rt_spin_lock_irqsave(&pdev->msi_lock); in msi_write_mask()
94 rt_pci_write_config_u32(pdev, msi->mask_pos, msi->mask); in msi_write_mask()
96 rt_spin_unlock_irqrestore(&pdev->msi_lock, level); in msi_write_mask()
101 rt_uint32_t mask, struct rt_pci_device *pdev) in msi_mask() argument
103 msi_write_mask(msi, 0, mask, pdev); in msi_mask()
107 rt_uint32_t mask, struct rt_pci_device *pdev) in msi_unmask() argument
109 msi_write_mask(msi, mask, 0, pdev); in msi_unmask()
112 static void msi_write_enable(struct rt_pci_device *pdev, rt_bool_t enable) in msi_write_enable() argument
116 rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); in msi_write_enable()
125 rt_pci_write_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, msgctl); in msi_write_enable()
133 struct rt_pci_device *pdev = desc->pdev; in msi_affinity_init() local
134 struct rt_pic *msi_pic = pdev->msi_pic; in msi_affinity_init()
179 void rt_pci_msi_shutdown(struct rt_pci_device *pdev) in rt_pci_msi_shutdown() argument
183 if (!pdev) in rt_pci_msi_shutdown()
188 msi_write_enable(pdev, RT_FALSE); in rt_pci_msi_shutdown()
189 rt_pci_intx(pdev, RT_TRUE); in rt_pci_msi_shutdown()
191 if ((desc = rt_pci_msi_first_desc(pdev))) in rt_pci_msi_shutdown()
193 msi_unmask(&desc->msi, msi_multi_mask(&desc->msi), pdev); in rt_pci_msi_shutdown()
197 pdev->irq = desc->msi.default_irq; in rt_pci_msi_shutdown()
198 pdev->msi_enabled = RT_FALSE; in rt_pci_msi_shutdown()
201 void rt_pci_msix_shutdown(struct rt_pci_device *pdev) in rt_pci_msix_shutdown() argument
205 if (!pdev) in rt_pci_msix_shutdown()
210 rt_pci_msi_for_each_desc(pdev, desc) in rt_pci_msix_shutdown()
215 msix_update_ctrl(pdev, PCIM_MSIXCTRL_MSIX_ENABLE, 0); in rt_pci_msix_shutdown()
217 rt_pci_intx(pdev, RT_TRUE); in rt_pci_msix_shutdown()
218 pdev->msix_enabled = RT_FALSE; in rt_pci_msix_shutdown()
221 void rt_pci_msi_free_irqs(struct rt_pci_device *pdev) in rt_pci_msi_free_irqs() argument
225 if (!pdev) in rt_pci_msi_free_irqs()
230 if (pdev->msix_base) in rt_pci_msi_free_irqs()
232 rt_iounmap(pdev->msix_base); in rt_pci_msi_free_irqs()
233 pdev->msix_base = RT_NULL; in rt_pci_msi_free_irqs()
236 rt_pci_msi_for_each_desc(pdev, desc) in rt_pci_msi_free_irqs()
257 struct rt_pci_device *pdev = desc->pdev; in rt_pci_msi_write_msg() local
290 int pos = pdev->msi_cap; in rt_pci_msi_write_msg()
293 rt_pci_read_config_u16(pdev, pos + PCIR_MSI_CTRL, &msgctl); in rt_pci_msi_write_msg()
296 rt_pci_write_config_u16(pdev, pos + PCIR_MSI_CTRL, msgctl); in rt_pci_msi_write_msg()
298 rt_pci_write_config_u32(pdev, pos + PCIR_MSI_ADDR, msg->address_lo); in rt_pci_msi_write_msg()
311 rt_pci_write_config_u32(pdev, pos + PCIR_MSI_ADDR_HIGH, msg->address_hi); in rt_pci_msi_write_msg()
312 rt_pci_write_config_u16(pdev, pos + PCIR_MSI_DATA_64BIT, msg->data); in rt_pci_msi_write_msg()
316 rt_pci_write_config_u16(pdev, pos + PCIR_MSI_DATA, msg->data); in rt_pci_msi_write_msg()
320 rt_pci_read_config_u16(pdev, pos + PCIR_MSI_CTRL, &msgctl); in rt_pci_msi_write_msg()
343 msi_mask(&desc->msi, RT_BIT(pirq->irq - desc->irq), desc->pdev); in rt_pci_msi_mask_irq()
360 msi_unmask(&desc->msi, RT_BIT(pirq->irq - desc->irq), desc->pdev); in rt_pci_msi_unmask_irq()
365 rt_ssize_t rt_pci_alloc_vector(struct rt_pci_device *pdev, int min, int max, in rt_pci_alloc_vector() argument
370 if (!pdev || min > max) in rt_pci_alloc_vector()
389 res = rt_pci_msix_enable_range_affinity(pdev, RT_NULL, min, max, affinities); in rt_pci_alloc_vector()
399 res = rt_pci_msi_enable_range_affinity(pdev, min, max, affinities); in rt_pci_alloc_vector()
409 if (min == 1 && pdev->irq >= 0) in rt_pci_alloc_vector()
417 rt_pic_irq_get_affinity(pdev->irq, old_affinity); in rt_pci_alloc_vector()
424 rt_pic_irq_set_affinity(pdev->irq, old_affinity); in rt_pci_alloc_vector()
427 rt_pci_intx(pdev, RT_TRUE); in rt_pci_alloc_vector()
436 void rt_pci_free_vector(struct rt_pci_device *pdev) in rt_pci_free_vector() argument
438 if (!pdev) in rt_pci_free_vector()
443 rt_pci_msi_disable(pdev); in rt_pci_free_vector()
444 rt_pci_msix_disable(pdev); in rt_pci_free_vector()
445 rt_pci_irq_mask(pdev); in rt_pci_free_vector()
448 static rt_err_t msi_verify_entries(struct rt_pci_device *pdev) in msi_verify_entries() argument
450 if (pdev->no_64bit_msi) in msi_verify_entries()
454 rt_pci_msi_for_each_desc(pdev, desc) in msi_verify_entries()
460 rt_dm_dev_get_name(&pdev->parent), in msi_verify_entries()
471 static rt_err_t msi_insert_desc(struct rt_pci_device *pdev, in msi_insert_desc() argument
496 msi_desc->pdev = pdev; in msi_insert_desc()
498 rt_list_insert_before(&pdev->msi_desc_nodes, &msi_desc->list); in msi_insert_desc()
503 rt_ssize_t rt_pci_msi_vector_count(struct rt_pci_device *pdev) in rt_pci_msi_vector_count() argument
507 if (!pdev) in rt_pci_msi_vector_count()
512 if (!pdev->msi_cap) in rt_pci_msi_vector_count()
517 rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); in rt_pci_msi_vector_count()
522 rt_err_t rt_pci_msi_disable(struct rt_pci_device *pdev) in rt_pci_msi_disable() argument
524 if (!pdev) in rt_pci_msi_disable()
529 if (!pdev->msi_enabled) in rt_pci_msi_disable()
534 spin_lock(&pdev->msi_lock); in rt_pci_msi_disable()
536 rt_pci_msi_shutdown(pdev); in rt_pci_msi_disable()
537 rt_pci_msi_free_irqs(pdev); in rt_pci_msi_disable()
539 spin_unlock(&pdev->msi_lock); in rt_pci_msi_disable()
544 static rt_err_t msi_setup_msi_desc(struct rt_pci_device *pdev, int nvec) in msi_setup_msi_desc() argument
552 desc.vector_count = rt_pci_msi_vector_count(pdev); in msi_setup_msi_desc()
555 rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &msgctl); in msi_setup_msi_desc()
572 desc.msi.mask_pos = pdev->msi_cap + PCIR_MSI_MASK_64BIT; in msi_setup_msi_desc()
576 desc.msi.mask_pos = pdev->msi_cap + PCIR_MSI_MASK; in msi_setup_msi_desc()
580 desc.msi.default_irq = pdev->irq; in msi_setup_msi_desc()
585 rt_pci_read_config_u32(pdev, desc.msi.mask_pos, &desc.msi.mask); in msi_setup_msi_desc()
588 return msi_insert_desc(pdev, &desc); in msi_setup_msi_desc()
591 static rt_ssize_t msi_capability_init(struct rt_pci_device *pdev, in msi_capability_init() argument
597 msi_write_enable(pdev, RT_FALSE); in msi_capability_init()
599 spin_lock(&pdev->msi_lock); in msi_capability_init()
601 if (!(err = msi_setup_msi_desc(pdev, nvec))) in msi_capability_init()
604 desc = rt_pci_msi_first_desc(pdev); in msi_capability_init()
605 msi_mask(&desc->msi, msi_multi_mask(&desc->msi), pdev); in msi_capability_init()
607 if (!(err = rt_pci_msi_setup_irqs(pdev, nvec, PCIY_MSI))) in msi_capability_init()
609 err = msi_verify_entries(pdev); in msi_capability_init()
614 msi_unmask(&desc->msi, msi_multi_mask(&desc->msi), pdev); in msi_capability_init()
618 spin_unlock(&pdev->msi_lock); in msi_capability_init()
622 rt_pci_msi_free_irqs(pdev); in msi_capability_init()
625 rt_dm_dev_get_name(&pdev->parent), "MSI", nvec, rt_strerror(err)); in msi_capability_init()
639 rt_pci_intx(pdev, RT_FALSE); in msi_capability_init()
642 msi_write_enable(pdev, RT_TRUE); in msi_capability_init()
644 pdev->irq = desc->irq; in msi_capability_init()
646 pdev->msi_enabled = RT_TRUE; in msi_capability_init()
651 rt_ssize_t rt_pci_msi_enable_range_affinity(struct rt_pci_device *pdev, in rt_pci_msi_enable_range_affinity() argument
657 if (!pdev || min > max) in rt_pci_msi_enable_range_affinity()
662 if (pdev->no_msi) in rt_pci_msi_enable_range_affinity()
667 if (!pdev->msi_pic) in rt_pci_msi_enable_range_affinity()
672 if (pdev->msi_enabled) in rt_pci_msi_enable_range_affinity()
674 LOG_W("%s: MSI is enabled", rt_dm_dev_get_name(&pdev->parent)); in rt_pci_msi_enable_range_affinity()
679 entries_nr = rt_pci_msi_vector_count(pdev); in rt_pci_msi_enable_range_affinity()
691 return msi_capability_init(pdev, nvec, affinities); in rt_pci_msi_enable_range_affinity()
694 rt_ssize_t rt_pci_msix_vector_count(struct rt_pci_device *pdev) in rt_pci_msix_vector_count() argument
698 if (!pdev) in rt_pci_msix_vector_count()
703 if (!pdev->msix_cap) in rt_pci_msix_vector_count()
708 rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); in rt_pci_msix_vector_count()
713 rt_err_t rt_pci_msix_disable(struct rt_pci_device *pdev) in rt_pci_msix_disable() argument
715 if (!pdev) in rt_pci_msix_disable()
720 if (!pdev->msix_enabled) in rt_pci_msix_disable()
725 spin_lock(&pdev->msi_lock); in rt_pci_msix_disable()
727 rt_pci_msix_shutdown(pdev); in rt_pci_msix_disable()
728 rt_pci_msi_free_irqs(pdev); in rt_pci_msix_disable()
730 spin_unlock(&pdev->msi_lock); in rt_pci_msix_disable()
735 static void *msix_table_remap(struct rt_pci_device *pdev, rt_size_t entries_nr) in msix_table_remap() argument
741 rt_pci_read_config_u32(pdev, pdev->msix_cap + PCIR_MSIX_TABLE, &table_offset); in msix_table_remap()
744 if (pdev->resource[bir].flags & PCI_BUS_REGION_F_NONE) in msix_table_remap()
746 LOG_E("%s: BAR[bir = %d] is invalid", rt_dm_dev_get_name(&pdev->parent), bir); in msix_table_remap()
751 table_base_phys = pdev->resource[bir].base + (table_offset & ~PCIM_MSIX_BIR_MASK); in msix_table_remap()
756 static rt_err_t msix_setup_msi_descs(struct rt_pci_device *pdev, in msix_setup_msi_descs() argument
765 desc.vector_count = rt_pci_msix_vector_count(pdev); in msix_setup_msi_descs()
780 if ((err = msi_insert_desc(pdev, &desc))) in msix_setup_msi_descs()
789 static rt_ssize_t msix_capability_init(struct rt_pci_device *pdev, in msix_capability_init() argument
806 msix_update_ctrl(pdev, 0, PCIM_MSIXCTRL_FUNCTION_MASK | PCIM_MSIXCTRL_MSIX_ENABLE); in msix_capability_init()
808 rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &msgctl); in msix_capability_init()
811 table_base = msix_table_remap(pdev, table_size); in msix_capability_init()
815 LOG_E("%s: Remap MSI-X table fail", rt_dm_dev_get_name(&pdev->parent)); in msix_capability_init()
821 pdev->msix_base = table_base; in msix_capability_init()
823 spin_lock(&pdev->msi_lock); in msix_capability_init()
825 if (!(err = msix_setup_msi_descs(pdev, table_base, entries, nvec))) in msix_capability_init()
827 if (!(err = rt_pci_msi_setup_irqs(pdev, nvec, PCIY_MSIX))) in msix_capability_init()
830 err = msi_verify_entries(pdev); in msix_capability_init()
834 spin_unlock(&pdev->msi_lock); in msix_capability_init()
838 rt_pci_msi_free_irqs(pdev); in msix_capability_init()
841 rt_dm_dev_get_name(&pdev->parent), "MSI-X", nvec, rt_strerror(err)); in msix_capability_init()
847 rt_pci_msi_for_each_desc(pdev, desc) in msix_capability_init()
859 rt_pci_intx(pdev, RT_FALSE); in msix_capability_init()
867 msix_update_ctrl(pdev, PCIM_MSIXCTRL_FUNCTION_MASK, 0); in msix_capability_init()
869 pdev->msix_enabled = RT_TRUE; in msix_capability_init()
874 msix_update_ctrl(pdev, PCIM_MSIXCTRL_FUNCTION_MASK | PCIM_MSIXCTRL_MSIX_ENABLE, 0); in msix_capability_init()
879 rt_ssize_t rt_pci_msix_enable_range_affinity(struct rt_pci_device *pdev, in rt_pci_msix_enable_range_affinity() argument
886 if (!pdev || min > max) in rt_pci_msix_enable_range_affinity()
891 if (pdev->no_msi) in rt_pci_msix_enable_range_affinity()
896 if (!pdev->msi_pic) in rt_pci_msix_enable_range_affinity()
901 if (pdev->msix_enabled) in rt_pci_msix_enable_range_affinity()
903 LOG_W("%s: MSI-X is enabled", rt_dm_dev_get_name(&pdev->parent)); in rt_pci_msix_enable_range_affinity()
908 entries_nr = rt_pci_msix_vector_count(pdev); in rt_pci_msix_enable_range_affinity()
941 rt_dm_dev_get_name(&pdev->parent), i, j); in rt_pci_msix_enable_range_affinity()
948 return msix_capability_init(pdev, entries, nvec, affinities); in rt_pci_msix_enable_range_affinity()