Lines Matching refs:index
65 int arm_gic_get_active_irq(rt_uint64_t index) in arm_gic_get_active_irq() argument
69 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
71 irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); in arm_gic_get_active_irq()
72 irq += _gic_table[index].offset; in arm_gic_get_active_irq()
76 void arm_gic_ack(rt_uint64_t index, int irq) in arm_gic_ack() argument
80 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
82 irq = irq - _gic_table[index].offset; in arm_gic_ack()
85 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
86 GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; in arm_gic_ack()
89 void arm_gic_mask(rt_uint64_t index, int irq) in arm_gic_mask() argument
93 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
95 irq = irq - _gic_table[index].offset; in arm_gic_mask()
98 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
101 void arm_gic_umask(rt_uint64_t index, int irq) in arm_gic_umask() argument
105 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
107 irq = irq - _gic_table[index].offset; in arm_gic_umask()
110 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
113 rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq) in arm_gic_get_pending_irq() argument
117 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
119 irq = irq - _gic_table[index].offset; in arm_gic_get_pending_irq()
124 pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_pending_irq()
129 … pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_pending_irq()
144 void arm_gic_set_pending_irq(rt_uint64_t index, int irq) in arm_gic_set_pending_irq() argument
146 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
148 irq = irq - _gic_table[index].offset; in arm_gic_set_pending_irq()
153 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); in arm_gic_set_pending_irq()
159 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); in arm_gic_set_pending_irq()
163 void arm_gic_clear_pending_irq(rt_uint64_t index, int irq) in arm_gic_clear_pending_irq() argument
167 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
169 irq = irq - _gic_table[index].offset; in arm_gic_clear_pending_irq()
175 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
180 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
184 void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config) in arm_gic_set_configuration() argument
189 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
191 irq = irq - _gic_table[index].offset; in arm_gic_set_configuration()
194 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
200 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
203 rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq) in arm_gic_get_configuration() argument
205 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_configuration()
207 irq = irq - _gic_table[index].offset; in arm_gic_get_configuration()
210 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
213 void arm_gic_clear_active(rt_uint64_t index, int irq) in arm_gic_clear_active() argument
217 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_active()
219 irq = irq - _gic_table[index].offset; in arm_gic_clear_active()
222 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
226 void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask) in arm_gic_set_cpu() argument
230 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_cpu()
232 irq = irq - _gic_table[index].offset; in arm_gic_set_cpu()
235 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); in arm_gic_set_cpu()
240 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; in arm_gic_set_cpu()
243 rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq) in arm_gic_get_target_cpu() argument
245 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_target_cpu()
247 irq = irq - _gic_table[index].offset; in arm_gic_get_target_cpu()
250 return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_target_cpu()
253 void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority) in arm_gic_set_priority() argument
257 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_priority()
259 irq = irq - _gic_table[index].offset; in arm_gic_set_priority()
262 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
265 GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_set_priority()
268 rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq) in arm_gic_get_priority() argument
270 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_priority()
272 irq = irq - _gic_table[index].offset; in arm_gic_get_priority()
275 return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_priority()
278 void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority) in arm_gic_set_interface_prior_mask() argument
280 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_interface_prior_mask()
283 GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; in arm_gic_set_interface_prior_mask()
286 rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index) in arm_gic_get_interface_prior_mask() argument
288 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_interface_prior_mask()
290 return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); in arm_gic_get_interface_prior_mask()
293 void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point) in arm_gic_set_binary_point() argument
295 GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; in arm_gic_set_binary_point()
298 rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index) in arm_gic_get_binary_point() argument
300 return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); in arm_gic_get_binary_point()
303 rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq) in arm_gic_get_irq_status() argument
308 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_irq_status()
310 irq = irq - _gic_table[index].offset; in arm_gic_get_irq_status()
313 active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
314 pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
319 void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_uint64_t filter_list) in arm_gic_send_sgi() argument
321 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_send_sgi()
323 irq = irq - _gic_table[index].offset; in arm_gic_send_sgi()
326 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = in arm_gic_send_sgi()
330 rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index) in arm_gic_get_high_pending_irq() argument
332 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_high_pending_irq()
334 return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); in arm_gic_get_high_pending_irq()
337 rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index) in arm_gic_get_interface_id() argument
339 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_interface_id()
341 return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); in arm_gic_get_interface_id()
344 void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group) in arm_gic_set_group() argument
349 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_group()
352 irq = irq - _gic_table[index].offset; in arm_gic_set_group()
355 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
360 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
363 rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq) in arm_gic_get_group() argument
365 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_group()
367 irq = irq - _gic_table[index].offset; in arm_gic_get_group()
370 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
373 int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start) in arm_gic_dist_init() argument
378 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_dist_init()
380 _gic_table[index].dist_hw_base = dist_base; in arm_gic_dist_init()
381 _gic_table[index].offset = irq_start; in arm_gic_dist_init()
449 int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base) in arm_gic_cpu_init() argument
451 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_cpu_init()
453 if (!_gic_table[index].cpu_hw_base) in arm_gic_cpu_init()
455 _gic_table[index].cpu_hw_base = cpu_base; in arm_gic_cpu_init()
457 cpu_base = _gic_table[index].cpu_hw_base; in arm_gic_cpu_init()
467 void arm_gic_dump_type(rt_uint64_t index) in arm_gic_dump_type() argument
471 gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); in arm_gic_dump_type()
473 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, in arm_gic_dump_type()
474 _gic_table[index].dist_hw_base, in arm_gic_dump_type()
480 void arm_gic_dump(rt_uint64_t index) in arm_gic_dump() argument
484 k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); in arm_gic_dump()
490 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
497 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
504 GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()