Lines Matching refs:x1
92 mov boot_arg0, x1
136 ldr x1, =rt_cpu_mpidr_table
138 add x1, x1, x2
145 ldr x3, [x1], #8
153 str x5, [x1, #-8]
164 mov x1, #ARCH_SECONDARY_CPU_STACK_SIZE
166 msub stack_top, x0, x1, x2
186 mov x1, #(1 << 0) /* EL0 and EL1 are in Non-Secure state */
187 orr x1, x1, #(1 << 4) /* RES1 */
188 orr x1, x1, #(1 << 5) /* RES1 */
189 orr x1, x1, #(1 << 10) /* The next lower level is AArch64 */
190 msr scr_el3, x1
192 mov x1, #9 /* Next level is 0b1001->EL2h */
193 orr x1, x1, #(1 << 6) /* Mask FIQ */
194 orr x1, x1, #(1 << 7) /* Mask IRQ */
195 orr x1, x1, #(1 << 8) /* Mask SError */
196 orr x1, x1, #(1 << 9) /* Mask Debug Exception */
197 msr spsr_el3, x1
199 get_phy x1, .init_cpu_hyp
200 msr elr_el3, x1
252 get_phy x1, __bss_start
254 sub x2, x2, x1 /* Get bss size */
262 str xzr, [x1], #8
268 strb wzr, [x1], #1
286 get_phy x1, .early_tbl1_page
296 get_phy x1, .early_tbl1_page
299 msr ttbr1_el1, x1
308 get_pvoff x1 x0
309 mov x1, stack_top
310 sub x1, x1, x0
311 mov sp, x1
316 mrs x1, sctlr_el1
317 orr x1, x1, #(1 << 12) /* Stage 1 instruction access Cacheability control */
318 orr x1, x1, #(1 << 2) /* Cacheable Normal memory in stage1 */
319 orr x1, x1, #(1 << 0) /* MMU Enable */
320 msr sctlr_el1, x1