Lines Matching refs:R0
252 LDR R0, =RSTC_BASE
254 STR R1, [R0, #RSTC_MR]
260 LDR R0, =EFC_BASE
262 STR R1, [R0, #EFC0_FMR]
267 LDR R0, =EFC_BASE
269 STR R1, [R0, #EFC1_FMR]
274 LDR R0, =WDT_BASE
276 STR R1, [R0, #WDT_MR]
282 LDR R0, =PMC_BASE
286 STR R1, [R0, #PMC_MOR]
290 MOSCS_Loop LDR R2, [R0, #PMC_SR]
298 STR R1, [R0, #PMC_PLLR]
301 PLL_Loop LDR R2, [R0, #PMC_SR]
310 STR R1, [R0, #PMC_MCKR]
311 WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
315 STR R1, [R0, #PMC_MCKR]
316 WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
322 STR R1, [R0, #PMC_MCKR]
323 WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
327 STR R1, [R0, #PMC_MCKR]
328 WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
340 LDMIA R8!, {R0-R7} ; Load Vectors
341 STMIA R9!, {R0-R7} ; Store Vectors
342 LDMIA R8!, {R0-R7} ; Load Handler Addresses
343 STMIA R9!, {R0-R7} ; Store Handler Addresses
353 LDR R0, =MC_BASE
355 STR R1, [R0, #MC_RCR] ; Remap
361 LDR R0, =Stack_Top
365 MOV SP, R0
366 SUB R0, R0, #UND_Stack_Size
370 MOV SP, R0
371 SUB R0, R0, #ABT_Stack_Size
375 MOV SP, R0
376 SUB R0, R0, #FIQ_Stack_Size
380 MOV SP, R0
381 SUB R0, R0, #IRQ_Stack_Size
385 MOV SP, R0
386 SUB R0, R0, #SVC_Stack_Size
397 ;MOV SP, R0
406 LDR R0, =__main
407 BX R0
492 LDR R0, = Heap_Mem