Lines Matching refs:index
63 int arm_gic_get_active_irq(rt_uint32_t index) in arm_gic_get_active_irq() argument
67 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
69 irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); in arm_gic_get_active_irq()
70 irq += _gic_table[index].offset; in arm_gic_get_active_irq()
74 void arm_gic_ack(rt_uint32_t index, int irq) in arm_gic_ack() argument
78 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
80 irq = irq - _gic_table[index].offset; in arm_gic_ack()
83 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
84 GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; in arm_gic_ack()
87 void arm_gic_mask(rt_uint32_t index, int irq) in arm_gic_mask() argument
91 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
93 irq = irq - _gic_table[index].offset; in arm_gic_mask()
96 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
99 void arm_gic_umask(rt_uint32_t index, int irq) in arm_gic_umask() argument
103 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
105 irq = irq - _gic_table[index].offset; in arm_gic_umask()
108 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
111 rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) in arm_gic_get_pending_irq() argument
115 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
117 irq = irq - _gic_table[index].offset; in arm_gic_get_pending_irq()
122 pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_pending_irq()
127 … pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_pending_irq()
142 void arm_gic_set_pending_irq(rt_uint32_t index, int irq) in arm_gic_set_pending_irq() argument
144 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
146 irq = irq - _gic_table[index].offset; in arm_gic_set_pending_irq()
151 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); in arm_gic_set_pending_irq()
157 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); in arm_gic_set_pending_irq()
161 void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) in arm_gic_clear_pending_irq() argument
165 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
167 irq = irq - _gic_table[index].offset; in arm_gic_clear_pending_irq()
173 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
178 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
182 void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config) in arm_gic_set_configuration() argument
187 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
189 irq = irq - _gic_table[index].offset; in arm_gic_set_configuration()
192 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
198 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
201 rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) in arm_gic_get_configuration() argument
203 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_configuration()
205 irq = irq - _gic_table[index].offset; in arm_gic_get_configuration()
208 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
211 void arm_gic_clear_active(rt_uint32_t index, int irq) in arm_gic_clear_active() argument
215 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_active()
217 irq = irq - _gic_table[index].offset; in arm_gic_clear_active()
220 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
224 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) in arm_gic_set_cpu() argument
228 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_cpu()
230 irq = irq - _gic_table[index].offset; in arm_gic_set_cpu()
233 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); in arm_gic_set_cpu()
238 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; in arm_gic_set_cpu()
241 rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) in arm_gic_get_target_cpu() argument
243 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_target_cpu()
245 irq = irq - _gic_table[index].offset; in arm_gic_get_target_cpu()
248 return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_target_cpu()
251 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) in arm_gic_set_priority() argument
255 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_priority()
257 irq = irq - _gic_table[index].offset; in arm_gic_set_priority()
260 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
263 GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_set_priority()
266 rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) in arm_gic_get_priority() argument
268 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_priority()
270 irq = irq - _gic_table[index].offset; in arm_gic_get_priority()
273 return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_priority()
276 void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) in arm_gic_set_interface_prior_mask() argument
278 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_interface_prior_mask()
281 GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; in arm_gic_set_interface_prior_mask()
284 rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) in arm_gic_get_interface_prior_mask() argument
286 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_interface_prior_mask()
288 return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); in arm_gic_get_interface_prior_mask()
291 void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) in arm_gic_set_binary_point() argument
293 GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; in arm_gic_set_binary_point()
296 rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) in arm_gic_get_binary_point() argument
298 return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); in arm_gic_get_binary_point()
301 rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) in arm_gic_get_irq_status() argument
306 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_irq_status()
308 irq = irq - _gic_table[index].offset; in arm_gic_get_irq_status()
311 active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
312 pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
317 void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list) in arm_gic_send_sgi() argument
319 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_send_sgi()
321 irq = irq - _gic_table[index].offset; in arm_gic_send_sgi()
324 …GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = ((filter_list & 0x3U) << 24U) | ((target_list &… in arm_gic_send_sgi()
327 rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) in arm_gic_get_high_pending_irq() argument
329 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_high_pending_irq()
331 return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); in arm_gic_get_high_pending_irq()
334 rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) in arm_gic_get_interface_id() argument
336 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_interface_id()
338 return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); in arm_gic_get_interface_id()
341 void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) in arm_gic_set_group() argument
346 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_group()
349 irq = irq - _gic_table[index].offset; in arm_gic_set_group()
352 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
357 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
360 rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) in arm_gic_get_group() argument
362 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_group()
364 irq = irq - _gic_table[index].offset; in arm_gic_get_group()
367 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
370 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) in arm_gic_dist_init() argument
375 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_dist_init()
377 _gic_table[index].dist_hw_base = dist_base; in arm_gic_dist_init()
378 _gic_table[index].offset = irq_start; in arm_gic_dist_init()
430 int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) in arm_gic_cpu_init() argument
432 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_cpu_init()
434 if (!_gic_table[index].cpu_hw_base) in arm_gic_cpu_init()
436 _gic_table[index].cpu_hw_base = cpu_base; in arm_gic_cpu_init()
438 cpu_base = _gic_table[index].cpu_hw_base; in arm_gic_cpu_init()
448 void arm_gic_dump_type(rt_uint32_t index) in arm_gic_dump_type() argument
452 gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); in arm_gic_dump_type()
454 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, in arm_gic_dump_type()
455 _gic_table[index].dist_hw_base, in arm_gic_dump_type()
461 void arm_gic_dump(rt_uint32_t index) in arm_gic_dump() argument
465 k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); in arm_gic_dump()
471 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
478 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
485 GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()