Lines Matching refs:irq
65 int irq; in arm_gic_get_active_irq() local
69 irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); in arm_gic_get_active_irq()
70 irq += _gic_table[index].offset; in arm_gic_get_active_irq()
71 return irq; in arm_gic_get_active_irq()
74 void arm_gic_ack(rt_uint32_t index, int irq) in arm_gic_ack() argument
76 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_ack()
80 irq = irq - _gic_table[index].offset; in arm_gic_ack()
81 RT_ASSERT(irq >= 0U); in arm_gic_ack()
83 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
84 GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; in arm_gic_ack()
87 void arm_gic_mask(rt_uint32_t index, int irq) in arm_gic_mask() argument
89 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_mask()
93 irq = irq - _gic_table[index].offset; in arm_gic_mask()
94 RT_ASSERT(irq >= 0U); in arm_gic_mask()
96 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
99 void arm_gic_umask(rt_uint32_t index, int irq) in arm_gic_umask() argument
101 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_umask()
105 irq = irq - _gic_table[index].offset; in arm_gic_umask()
106 RT_ASSERT(irq >= 0U); in arm_gic_umask()
108 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
111 rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) in arm_gic_get_pending_irq() argument
117 irq = irq - _gic_table[index].offset; in arm_gic_get_pending_irq()
118 RT_ASSERT(irq >= 0U); in arm_gic_get_pending_irq()
120 if (irq >= 16U) in arm_gic_get_pending_irq()
122 pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_pending_irq()
127 … pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_pending_irq()
142 void arm_gic_set_pending_irq(rt_uint32_t index, int irq) in arm_gic_set_pending_irq() argument
146 irq = irq - _gic_table[index].offset; in arm_gic_set_pending_irq()
147 RT_ASSERT(irq >= 0U); in arm_gic_set_pending_irq()
149 if (irq >= 16U) in arm_gic_set_pending_irq()
151 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); in arm_gic_set_pending_irq()
157 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); in arm_gic_set_pending_irq()
161 void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) in arm_gic_clear_pending_irq() argument
167 irq = irq - _gic_table[index].offset; in arm_gic_clear_pending_irq()
168 RT_ASSERT(irq >= 0U); in arm_gic_clear_pending_irq()
170 if (irq >= 16U) in arm_gic_clear_pending_irq()
172 mask = 1U << (irq % 32U); in arm_gic_clear_pending_irq()
173 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
177 mask = 1U << ((irq % 4U) * 8U); in arm_gic_clear_pending_irq()
178 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
182 void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config) in arm_gic_set_configuration() argument
189 irq = irq - _gic_table[index].offset; in arm_gic_set_configuration()
190 RT_ASSERT(irq >= 0U); in arm_gic_set_configuration()
192 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
193 shift = (irq % 16U) << 1U; in arm_gic_set_configuration()
198 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
201 rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) in arm_gic_get_configuration() argument
205 irq = irq - _gic_table[index].offset; in arm_gic_get_configuration()
206 RT_ASSERT(irq >= 0U); in arm_gic_get_configuration()
208 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
211 void arm_gic_clear_active(rt_uint32_t index, int irq) in arm_gic_clear_active() argument
213 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_clear_active()
217 irq = irq - _gic_table[index].offset; in arm_gic_clear_active()
218 RT_ASSERT(irq >= 0U); in arm_gic_clear_active()
220 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
224 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) in arm_gic_set_cpu() argument
230 irq = irq - _gic_table[index].offset; in arm_gic_set_cpu()
231 RT_ASSERT(irq >= 0U); in arm_gic_set_cpu()
233 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); in arm_gic_set_cpu()
235 old_tgt &= ~(0x0FFUL << ((irq % 4U)*8U)); in arm_gic_set_cpu()
236 old_tgt |= cpumask << ((irq % 4U)*8U); in arm_gic_set_cpu()
238 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; in arm_gic_set_cpu()
241 rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) in arm_gic_get_target_cpu() argument
245 irq = irq - _gic_table[index].offset; in arm_gic_get_target_cpu()
246 RT_ASSERT(irq >= 0U); in arm_gic_get_target_cpu()
248 return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_target_cpu()
251 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) in arm_gic_set_priority() argument
257 irq = irq - _gic_table[index].offset; in arm_gic_set_priority()
258 RT_ASSERT(irq >= 0U); in arm_gic_set_priority()
260 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
261 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
262 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
263 GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_set_priority()
266 rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) in arm_gic_get_priority() argument
270 irq = irq - _gic_table[index].offset; in arm_gic_get_priority()
271 RT_ASSERT(irq >= 0U); in arm_gic_get_priority()
273 return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_priority()
301 rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) in arm_gic_get_irq_status() argument
308 irq = irq - _gic_table[index].offset; in arm_gic_get_irq_status()
309 RT_ASSERT(irq >= 0U); in arm_gic_get_irq_status()
311 active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
312 pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
317 void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list) in arm_gic_send_sgi() argument
321 irq = irq - _gic_table[index].offset; in arm_gic_send_sgi()
322 RT_ASSERT(irq >= 0U); in arm_gic_send_sgi()
324 …].dist_hw_base) = ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL); in arm_gic_send_sgi()
341 void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) in arm_gic_set_group() argument
349 irq = irq - _gic_table[index].offset; in arm_gic_set_group()
350 RT_ASSERT(irq >= 0U); in arm_gic_set_group()
352 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
353 shift = (irq % 32U); in arm_gic_set_group()
357 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
360 rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) in arm_gic_get_group() argument
364 irq = irq - _gic_table[index].offset; in arm_gic_get_group()
365 RT_ASSERT(irq >= 0U); in arm_gic_get_group()
367 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()