Lines Matching refs:dist_hw_base
28 rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ member
94 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
115 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
130 pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_pending_irq()
135 … pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_pending_irq()
159 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); in arm_gic_set_pending_irq()
165 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); in arm_gic_set_pending_irq()
181 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
186 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
200 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
206 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
216 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
228 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
241 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); in arm_gic_set_cpu()
246 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; in arm_gic_set_cpu()
256 return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_target_cpu()
280 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
283 GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_set_priority()
303 return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_priority()
372 active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
373 pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
440 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
445 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
455 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
475 base = _gic_table[index].dist_hw_base; in arm_gicv3_wait_rwp()
494 _gic_table[index].dist_hw_base = dist_base; in arm_gic_dist_init()
662 gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); in arm_gic_dump_type()
664 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, in arm_gic_dump_type()
665 _gic_table[index].dist_hw_base, in arm_gic_dump_type()
681 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
688 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
695 GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()